CN114328322B - DMA controller operation method capable of configuring function mode - Google Patents
DMA controller operation method capable of configuring function mode Download PDFInfo
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- CN114328322B CN114328322B CN202210261057.1A CN202210261057A CN114328322B CN 114328322 B CN114328322 B CN 114328322B CN 202210261057 A CN202210261057 A CN 202210261057A CN 114328322 B CN114328322 B CN 114328322B
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Abstract
The invention relates to the technical field of data transmission, in particular to a DMA controller operation method capable of configuring a function mode.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a DMA controller operation method capable of configuring a function mode.
Background
The DMA (Direct Memory Access) mode is a data transmission mode for directly completing data transfer between a system Memory and an external device, and since the transmission process is performed by hardware, only the transmission is required to be intervened by a processor at the beginning and the end, and a large amount of processors are not required to intervene and schedule, so that the DMA mode is mainly used for high-speed transmission of a large amount of data, and can effectively reduce the data transmission time and reduce the operation load of the processor. And during the data transmission of the DMA, the processor can execute other tasks, so that the running efficiency of the processor can be improved.
However, after receiving a primary initiation instruction from the processor, the current DMA controller generally can only perform a data transmission from the memory to the external device or from the external device to the memory once, and due to the increase of the processing requirements for images, audio, video, and the like, the requirement for performing the same processing on a large amount of data is increasing, and if the external device needs to read data from the memory to a specific external device for many times and then stores the data back to the system memory after completing the data processing, the current DMA controller design still needs to perform a plurality of times of processor initiation/completion DMA data transmission instructions, which affects the processor efficiency and the data transmission speed.
Disclosure of Invention
In order to solve the above technical problems in the prior art, the present invention provides a DMA controller operation method capable of configuring a functional mode, and the specific technical solution is as follows:
a DMA controller operation method capable of configuring functional modes is applied to an SOC system on chip and comprises the following steps:
after initializing the system, the processor completes configuration of information required by a carrying and execution mode by writing configuration information into a corresponding memory mapping register;
step two, the processor initiates an instruction by writing the operation information into a corresponding memory mapping register, the DMA controller judges whether the DMA controller is in a configuration mode, if not, the DMA controller feeds back the access success, and then the processor judges a carrying and execution mode;
if the DMA controller enters a carrying mode, firstly, the DMA controller determines data input by reading a data transmission direction register, and finishes data carrying from the peripheral to the memory or in the opposite direction according to the input direction;
and step four, if the execution mode is entered, writing the initial address of the memory into the current address register of the memory, writing the initial address of the target memory into the target current address register, controlling the memory and the peripheral equipment to carry out data interaction by the DMA controller according to the written configuration information, starting the peripheral equipment to carry out data processing until all target data in the memory are processed by the peripheral equipment, and writing all results back to the target address of the memory.
Further, the step one specifically includes:
step 1.1, after the system is initialized, all configuration information registers are initialized to be 0, and the processor tries to enter a configuration mode;
step 1.2, in order to enter the configuration mode, the processor writes 1 into the configuration progress status register;
step 1.3, when trying to write, the DMA controller judges the self idle state, namely, reads the existing numerical value of the operating state register, if the numerical value is 0, the DMA controller feeds back the success of the access and the write, and enters a configuration mode; and if the numerical value is 1, the DMA controller feeds back the failure of access and write-in to the processor.
And step 1.4, after entering the configuration mode, the processor writes configuration information into the corresponding memory mapping register according to the requirement, the address which is not needed is vacated, after the completion, 0 is written into the configuration progress status register, and the configuration mode is exited.
Further, the second step specifically includes:
step 2.1, the processor initiates an instruction corresponding to the memory mapping register through writing the running information, and when the instruction is executed, the DMA controller judges whether the DMA controller is in a configuration mode, namely, the existing numerical value of the configuration execution state register is checked, and if the numerical value is 0, the memory access and writing are fed back to be successful; if the numerical value is 1, the DMA controller feeds back the failure of access and memory writing to the processor;
step 2.2, if the feedback access writing is successful, the processor writes 1 into the data valid state register, the DMA controller enters mode judgment, pulls down the completion state register, writes 0 into the error state register, and activates the comparison module;
step 2.3, after the mode judgment is entered, the DMA controller checks that the initial address of the corresponding memory of the peripheral or the initial address of the target memory is 0, then the DMA controller enters the carrying mode judgment and writes 0 into the mode judgment register; otherwise, the execution mode judgment is performed, and 1 is written into the mode judgment register.
Further, the entering the transportation mode is specifically:
the comparison module judges the following conditions: checking all values of the transport mode register, if any value is 0, sending an interrupt to the processor by the DMA controller, changing an error state register into 1, and finishing the pull-up of the state register; after the judgment is passed, comparing the initial address of the memory of the system memory in the transport mode with the initial address of the system memory, wherein the initial address of the memory of the system memory is less than or equal to the initial address of the memory of the system memory; then, calculating the sum of the initial address and the initial data size of the system memory by using an adder, and calculating the tail address of the memory of the system memory in the transport mode, wherein the former address is less than or equal to the latter address; when any condition is not met, the DMA controller sends an interrupt to the processor, changes the error state register to 2 and completes the pull-up of the state register; and if the conditions are met, checking the initial data size register, if the numerical value is 0, sending an interrupt to the processor by the DMA controller, changing the error state register into 4, and pulling up the state register.
Further, the entering the execution mode is specifically:
the comparison module makes the following determinations: checking all the values of the execution mode register, if all the types have at least one value of 0, the DMA controller sends an interrupt to the processor, changes the error state register into 1, and finishes the pull-up of the state register; the starting address of the memory corresponding to the peripheral is sequentially matched with the starting address of the memory corresponding to the peripheral in the execution mode, if the address cannot be matched with any configuration address, the DMA controller sends an interrupt to the processor, the error state register is changed into 3, and the state register is pulled up; if the matching is successful, if the matching success type is 1, writing 1 into the matching type register, wherein the related information in the following steps corresponds to the type 1; then checking registers of the initial data size and the target data size, if any numerical value is 0, the DMA controller sends an interrupt to the processor, the error state register is changed to 4, and the state register is pulled up; and if the judgment is passed, checking whether the system memory address meets the preset configuration range.
Further, the third step specifically includes: if the DMA controller enters the carrying mode, the DMA controller determines data input by reading a data transmission direction register, namely: if the state is 0, transmitting the peripheral to the memory; if the state is 1, the memory is transmitted to the external device, the initial address of the memory is written into the current address register of the memory, and the initial data size is written into the memory and the residual data size register of the external device.
Further, if the peripheral device is in a transmission state to the memory, writing data into an FIFO buffer memory when the data of the peripheral interface is valid and the FIFO is not full, updating the size of the residual data of the peripheral device, sequentially writing tail data in the buffer memory into the memory by taking the address of the current memory as a target when the FIFO is not empty, sending a ready signal to the peripheral interface by a DMA controller when the FIFO is not full, clearing the corresponding data out of the FIFO when the memory feeds back that the writing is successful, updating the address of the current memory and the size of the residual data of the memory, judging whether the size of the residual data is 0 or not, and repeating the process if the size of the residual data is not 0; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller restores the idle state.
Further, if the transmission state is from the memory to the peripheral, when the FIFO is not full, a reading request is sent to the memory by taking the current memory address as a target, if the reading is successful, the acquired data is written into the FIFO, the current memory address and the size of the residual data of the memory are updated, and meanwhile, whether the size of the residual data is 0 or not is judged, if not, the process is repeated; otherwise, stopping data reading; meanwhile, when the FIFO is not fully empty and the peripheral interface receives a ready signal, the tail end data is cleared out of the FIFO, written into the peripheral interface and pulled up the interface valid signal, and the size of the peripheral residual data is updated and whether the size is 0 or not is judged, if not, the process is repeated; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller restores the idle state.
Further, the fourth step specifically includes:
step 4.1, after entering the configuration state of the execution mode, finding the configuration information corresponding to the peripheral equipment through the matching type register, sequentially writing the information into the memory mapping register of the corresponding peripheral equipment through a memory access instruction, and judging the transmission completion condition of the configuration information by updating the size of the residual data of the configuration information; meanwhile, a required data transmission number register is calculated according to the initial data size and the single-transmission initial data size, and the single-transmission initial data size is written into a residual data size register;
step 4.2, waiting for a ready signal fed back by the peripheral interface, entering an execution mode writing state after the signal is pulled up, sequentially reading the data of the memory into the FIFO cache, sequentially writing the data at the tail end of the FIFO into the peripheral interface, and updating a register of the address of the memory, the size of the residual data of the memory and the size of the residual data of the peripheral;
step 4.3, waiting for the peripheral interface to feed back a valid signal, entering an execution mode reading state after the signal is pulled up, and writing the target data size into a memory and a peripheral residual data size register; reading the peripheral interface data into an FIFO cache in sequence after obtaining the feedback, writing the FIFO tail end data into the memory in sequence by taking the current target memory address as a target, and updating the target current address, the size of the residual data of the memory and the size register of the peripheral residual data;
4.4, updating the required data transmission frequency register and judging whether the register result is 0, if not, repeating the steps 4.1 to 4.3; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller returns to the idle state.
Has the advantages that:
the invention can directly access the memory during data transmission control, and adds an execution mode under the condition of keeping the data carrying function of the prior DMA controller, the data can be automatically read from the system memory to the specific memory mapping external equipment for many times during the mode operation, the external equipment is stored back to the specific system storage space after finishing the data processing, and the DMA controller does not need the intervention of a processor during the mode operation except the entering and exiting modes.
Drawings
FIG. 1 is a schematic structural diagram of a DMA controller of the present invention applied to a SOC chip;
fig. 2 a-2 c are schematic diagrams of the operation of the DMA controller of the present invention.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
The invention provides a DMA controller operation method capable of configuring functional mode, which adds an execution mode under the condition of keeping the existing DMA data carrying mode, can automatically read data from a system memory to a specific memory mapping external device for many times when the execution mode operates, stores the data back to a specific system storage space after the external device completes data processing, and does not need processor intervention when the DMA controller operates in the execution mode except the entering and exiting modes.
Specifically, as shown in fig. 1, the DMA controller is implemented in an SOC system on chip and is accessed to a system bus as a memory mapped IO device to ensure that a processor can read and write information through a memory mapped register. The peripheral interface comprises a data IO interface and two pairs of valid/ready handshake signals, wherein one pair is in the direction from the DMA controller to the outside, and the other pair is in the direction from the outside to the DMA controller.
The execution mode may set multiple types, where in this embodiment of the present invention, the type is set to 2, it is assumed that the system address is represented by 32 bits, the word is represented by 64 bits, it is assumed that the data port in the peripheral interface is 64 bits, and the start address of the available memory mapped address space is 0x6000000, where the assignable address is as in table 1, where table 1 is a DMA controller memory mapped address assignment method provided according to an exemplary embodiment of the present invention.
The peripheral configuration information format corresponding to each type is shown in table 2, and is considered as a register array, each array unit is shown as an address + numerical value format, the array size of each type in the embodiment of the present invention is 8, and the bit width of each unit is 96 bits. The data size of the peripheral configuration information of the execution mode is used for representing the number of effective units in the corresponding number sequence, and the effective numbers are 1-8 in the embodiment of the invention.
The information required by the DMA controller to configure the transport mode comprises the following information: the memory address field of the system memory is configured with the proceeding state.
The DMA controller configures information required for an execution mode, including: the method comprises the steps of a system memory address field, a memory initial address corresponding to an external device, a single initial data transmission size, configuration information corresponding to the external device and configuration information data size. The DMA controller may have one or more type intervals, each containing the above information.
The information written by the processor required by the DMA controller to initiate the transport mode comprises: the system memory initial address, the initial data size, the data transfer direction and the data valid state.
The DMA controller initiates information written by the processor required for the execution mode, including: the system memory initial address, the peripheral corresponding memory initial address, the target memory initial address, the initial data size, the target data size and the data valid state, wherein the system memory initial address, the initial data size and the data valid state memory mapping register are shared with the transport mode.
The DMA controller is provided with a read-only register which represents an operation state and an error state and is used for the processor to judge the DMA operation condition.
The DMA controller is a hardware module required by the realization process, and comprises: the device comprises all memory mapping registers used for corresponding to the table 1, FIFO (first in first out) cache used for temporarily storing transmission data, an adder used for calculating address change, a subtracter used for calculating the size of residual data and the number of required data transmission times, a divider used for calculating the number of data transmission times, a state machine used for controlling the flow of a DMA (direct memory access) controller, registers used for judging the storage mode, the matching type, the current memory address corresponding to the peripheral, the current target memory address and the size of the residual data of the memory, the peripheral and configuration information, a register used for recording the matching interval of the execution mode and a comparison module used for comparing the address section and the input address in the configuration information.
As shown in fig. 2 a-2 c, a method for operating a DMA controller with configurable functional modes includes the following steps:
initializing a system, initializing all configuration information registers to be 0, completing configuration of information required by a carrying and execution mode by a processor through writing in a corresponding memory mapping register before calling a DMA controller, if any configuration information is 0 or the execution mode is configuration information of at least one type and is not 0, the corresponding mode cannot be started, if the processor initiates a mode instruction in the period, the DMA controller sends an interrupt to the processor, and an error state register is changed to be 1; before starting to change the configuration information, writing 1 in a configuration status address, after the configuration is finished, writing 0 in the same address, changing an error status register into 0, releasing DMA, and if the processor sends a mode initiation instruction when the address is not 0, failing to write feedback; during the DMA idle period, the configuration information can be changed again through the processor; during the DMA operation, the processor cannot change the mode configuration register, so if the processor issues a change instruction, the feedback write fails. More specifically, the method comprises the following steps:
step 1.1, when a system is initialized, all the memory mapping registers mentioned in the table 1 are initialized to be 0; before a processor initiates an instruction, namely writing information into an address field of 0x600000d 7-0 x600000e8, entering a configuration mode, and writing necessary configuration information into the address field of 0x 60000000-0 x600000d 5;
step 1.2, in order to enter the configuration mode, the processor writes 1 into a configuration progress status register, namely, the address 0x600000d 6;
step 1.3, when trying to write, the DMA controller judges the self idle state, namely, reads the existing numerical value of the operating state register, if the numerical value is 0, the DMA controller feeds back the success of the access and the write, and enters a configuration mode; and if the numerical value is 1, the DMA controller feeds back the failure of access and write-in to the processor.
Step 1.4, after entering the configuration mode, the processor writes configuration information into the address field of 0x 60000000-0 x600000d5 as required, the unneeded address is vacated, after the completion, writes 0 into the configuration progress status register 0x600000d6, and exits the configuration mode.
Step two, the processor initiates an instruction through writing the operation information corresponding to the memory mapping register, the DMA controller judges whether the processor is in a configuration mode during the operation, if not, the DMA controller feeds back the access success, and then the processor judges the carrying and execution mode, specifically comprising the following steps:
step 2.1, when the processor needs to initiate a DMA instruction, writing information into the address field of 0x600000d 7-0 x600000e8 as required, and leaving out an unnecessary address; meanwhile, the DMA controller judges whether the DMA controller is in a configuration mode, namely, the DMA controller checks the existing numerical value of the configuration progress status register, and if the numerical value is 0, the DMA controller feeds back that the access and the write-in are successful; and if the numerical value is 1, the DMA controller feeds back the access and write failure to the processor.
And 2.2, if the feedback memory access writing is successful, the processor writes 1 into a data valid state register, namely an address 0x600000e8, the DMA controller enters mode judgment, pulls down the completion state register, writes 0 into the error state register, and activates the comparison module.
Step 2.3, after the mode judgment is entered, the DMA controller checks that the initial address of the corresponding memory of the peripheral or the initial address of the target memory is 0, then the DMA controller enters the carrying mode judgment and writes 0 into the mode judgment register; otherwise, the execution mode judgment is performed, and 1 is written into the mode judgment register.
And 2.4, entering a carrying mode for judgment, checking the numerical values of all carrying mode registers by the comparison module, if any numerical value is 0, sending an interrupt to the processor by the DMA controller, changing the error state register into 1, and finishing the state register pull-up. After the judgment is passed, comparing the initial address of the memory of the system memory in the transport mode with the initial address of the system memory, wherein the initial address of the memory of the system memory is less than or equal to the initial address of the memory of the system memory; and then calculating the sum of the initial address of the system memory and the initial data size and the tail address of the memory of the system memory in the transport mode by using an adder, wherein the former address is less than or equal to the latter address. If any of the above conditions is not met, the DMA controller sends an interrupt to the processor, changes the error status register to 2, and completes the status register pull-up. And if the conditions are met, checking the initial data size register, if the numerical value is 0, sending an interrupt to the processor by the DMA controller, changing the error state register into 4, and pulling up the state register.
And 2.5, entering execution mode judgment, checking the numerical values of all execution mode registers by the comparison module, if at least one numerical value of all types is 0, sending an interrupt to the processor by the DMA controller, changing the error state register into 1, and finishing the state register pull-up. And sequentially matching the initial address of the memory corresponding to the peripheral equipment and the initial address of the memory corresponding to the peripheral equipment in the execution mode, and if the address cannot be matched with any one of the configuration addresses, sending an interrupt to the processor by the DMA controller, changing the error state register into 3, and pulling up the state register. If the matching is successful, if the matching success type is 1, writing 1 into the matching type register, and the related information in the following steps corresponds to the type 1. And then checking the registers of the initial data size and the target data size, if any numerical value is 0, the DMA controller sends an interrupt to the processor, the error state register is changed into 4, and the state register is pulled up. If the judgment is passed, whether the system memory address meets the preset configuration range or not is checked, and the method is the same as the step 2.4.
And step three, if the DMA controller enters a carrying mode, the DMA controller determines data input by reading the data transmission direction register, and carries data from the peripheral to the memory or in the opposite direction according to the input direction. If the state is 0, the peripheral device transmits to the memory; if the state is 1, namely the memory transmits to the peripheral, the initial address of the memory is written into the current address register of the memory, and the initial data size is written into the memory and the residual data size register of the peripheral. The method specifically comprises the following steps:
and 3.1, if the transmission state of the peripheral to the memory is in a state of transmitting the peripheral to the memory, the DMA controller pulls up a peripheral interface ready signal when the FIFO is not full. And the DMA controller writes interface data into the FIFO cache head end when the external interface valid is 1 and the FIFO is not full, and updates the head end pointer and the size of the external residual data. In the present example, the size of the peripheral remaining data is reduced by 8 every time the writing is successful, and it is determined whether the size of the peripheral remaining data is 0 every clock cycle, if yes, the data writing into the FIFO is stopped and the peripheral interface ready signal is pulled low. Meanwhile, when the FIFO is not empty, the DMA controller writes the tail data in the cache into the memory by taking the current memory address as a target, and meanwhile, when the memory feedback is successfully written, the tail pointer of the FIFO is updated, and the current memory address and the size of the residual data of the memory are updated, namely the current memory address is increased by 8, and the size of the residual data of the memory is decreased by 8. Meanwhile, the DMA controller judges whether the size of the residual data of the memory is 0 after each update. If not, repeating the process; otherwise, the DMA controller stops sending the data writing request to the memory, sends an interrupt to the processor, pulls up the completion status register, clears the memory mapping registers with all addresses within the interval of 0x600000d 7-0 x600000e8, and restores the idle state.
And 3.2, if the memory is in an externally-arranged transmission state, the DMA controller needs to pull up a valid signal of an external interface when the FIFO is not fully empty, sends a reading request to the memory by taking the current memory address as a target when the FIFO is not fully full, writes the acquired data into the head end of the FIFO if the reading is successful, updates a head end pointer and updates the current memory address and the size of the residual data of the memory, namely adding 8 to the current memory address, reducing 8 to the size of the residual data of the memory, and judges whether the size of the residual data is 0 or not in each clock cycle. If not, repeating the above process; otherwise, the data reading request is stopped from being sent to the memory. Meanwhile, the DMA controller writes the tail end data of the FIFO cache into the peripheral interface, the writing is considered to be successful when the FIFO is not completely empty and the ready signal of the peripheral interface is 1, the tail end pointer is updated, and the size of the peripheral residual data is updated, namely the size of the peripheral residual data is reduced by 8. Meanwhile, whether the size of the peripheral residual data is 0 is judged in each clock period. If not, repeating the process; otherwise, the DMA controller pulls down the peripheral interface valid signal and sends an interrupt to the processor, pulls up the completion status register, clears all the memory mapping registers with the addresses within the interval of 0x600000d 7-0 x600000e8, and restores the idle state.
And step four, if the execution mode is entered, writing the initial address of the memory into the current address register of the memory, writing the initial address of the target memory into the target current address register, controlling the memory and the peripheral equipment to carry out data interaction by the DMA controller according to the written configuration information, starting the peripheral equipment to carry out data processing until all target data in the memory are processed by the peripheral equipment, and writing all results back to the target address of the memory. In this example, data in the execution mode single transfer initial data size is written to the memory and peripheral remaining data size registers. And writing the data size of the peripheral configuration information in the execution mode into a required data transmission frequency register, and entering an execution mode configuration state. The method specifically comprises the following steps:
and 4.1, after entering an execution mode configuration state, checking the matching type register by the DMA controller, determining a matching number sequence according to the value of the matching type register, reading a unit of the number of the register value minus 1 corresponding to the required data transmission times in the number sequence, taking the first 32 bits of the number as an address and the last 64 bits as data, and sending a memory access and write request to a system bus. And when the bus feedback writing is successful, the required data transmission times are reduced by 1. And meanwhile, the required data transmission times are judged in each clock period, when the value is 0, the memory access request is stopped being sent, and the peripheral interface ready signal is waited to be pulled high. In the embodiment, a divider is used to calculate the initial data size divided by the initial data size of a single transfer in the execution mode, and the required data transfer number register is written.
And 4.2, after a peripheral interface ready signal is pulled up, entering an execution mode writing state, sequentially reading the memory data into an FIFO cache, sequentially writing the FIFO tail end data into the peripheral interface, updating registers of a memory address, the size of the residual data of the memory and the size of the residual data of the peripheral, and performing the same mode as the step 3.2 except that the DMA does not send an interrupt and does not change various registers. And after the completion, waiting for the pulling-high of the valid signal of the peripheral interface.
And 4.3, after the valid signal of the peripheral interface is pulled up, entering an execution mode reading state. And writing the target data size register data into the memory and the peripheral residual data size register. The DMA controller reads the peripheral interface data into the FIFO cache in sequence, writes the FIFO tail data into the memory in sequence by taking the current target memory address as a target, updates the target current address, the size of the residual data of the memory and the size of the peripheral residual data registers, and adopts the same mode as the step 3.1 except that the DMA does not send interrupt and does not change various registers. After the completion, the required data transmission number register is updated, i.e. the value is reduced by 1.
And 4.4, after the execution mode reading state is entered, judging whether the size of the residual data of the memory and the register value of the required data transmission times are 0 or not in each clock cycle. If the size of the residual data of the memory is 0 and the value of the required data transmission times register is not 0, entering an execution mode configuration state, and repeating the steps 4.1-4.3; if the two items are 0 at the same time, the DMA controller pulls down a peripheral interface ready signal and sends an interrupt to the processor, pulls up a completion status register, clears all the memory mapping registers with the addresses within the interval of 0x600000d 7-0 x600000e8, and restores the idle state.
Table 1:
table 2:
the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the foregoing has described the practice of the present invention in detail, it will be apparent to those skilled in the art that modifications may be made to the practice of the invention as described in the foregoing examples, or that certain features may be substituted in the practice of the invention. All changes, equivalents and modifications which come within the spirit and scope of the invention are desired to be protected.
Claims (8)
1. A DMA controller operation method capable of configuring functional modes is applied to an SOC (system on chip), and is characterized by comprising the following steps:
after initializing the system, the processor completes configuration of information required by a carrying and execution mode by writing configuration information into a corresponding memory mapping register;
step two, the processor initiates an instruction by writing the operation information into a corresponding memory mapping register, the DMA controller judges whether the DMA controller is in a configuration mode, if not, the DMA controller feeds back the access success, and then the processor judges a carrying and execution mode;
if the DMA controller enters a carrying mode, firstly, the DMA controller determines data input by reading a data transmission direction register, and finishes data carrying from the peripheral to a memory or in the opposite direction according to the input direction;
step four, if entering the execution mode, writing the initial address of the memory into the address register of the current memory, writing the initial address of the target memory into the current address register of the target, controlling the memory and the peripheral equipment to perform data interaction according to the written configuration information by the DMA controller, starting the peripheral equipment to perform data processing until all target data in the memory are processed by the peripheral equipment, and writing all results back to the target address of the memory, specifically comprising:
step 4.1, after entering the configuration state of the execution mode, finding out the configuration information corresponding to the peripheral equipment through a matching type register, sequentially writing the information into a memory mapping register of the corresponding peripheral equipment through a memory access instruction, and judging the transmission completion condition of the configuration information through updating the size of the residual data of the configuration information; meanwhile, a required data transmission number register is calculated according to the initial data size and the single-transmission initial data size, and the single-transmission initial data size is written into a residual data size register;
step 4.2, waiting for a ready signal fed back by the peripheral interface, entering an execution mode writing state after the signal is pulled up, sequentially reading the data of the memory into the FIFO cache, sequentially writing the data at the tail end of the FIFO into the peripheral interface, and updating a register of the address of the memory, the size of the residual data of the memory and the size of the residual data of the peripheral;
step 4.3, waiting for the peripheral interface to feed back a valid signal, entering an execution mode reading state after the signal is pulled up, and writing the target data size into a memory and a peripheral residual data size register; reading the peripheral interface data into an FIFO cache in sequence after obtaining the feedback, writing the FIFO tail end data into the memory in sequence by taking the current target memory address as a target, and updating the target current address, the size of the residual data of the memory and the size register of the peripheral residual data;
4.4, updating the required data transmission frequency register and judging whether the register result is 0, if not, repeating the steps 4.1 to 4.3; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller returns to the idle state.
2. The method according to claim 1, wherein the step one specifically comprises:
step 1.1, after the system is initialized, all configuration information registers are initialized to be 0, and a processor tries to enter a configuration mode;
step 1.2, in order to enter the configuration mode, the processor writes 1 into the configuration progress status register;
step 1.3, when trying to write, the DMA controller judges the self idle state, namely, reads the existing numerical value of the operating state register, if the numerical value is 0, the DMA controller feeds back the success of the access and the write, and enters a configuration mode; if the numerical value is 1, the DMA controller feeds back the failure of access and memory writing to the processor;
and step 1.4, after entering the configuration mode, the processor writes configuration information into the corresponding memory mapping register according to the requirement, the address which is not needed is vacated, after the completion, 0 is written into the configuration progress status register, and the configuration mode is exited.
3. The method for operating a DMA controller with configurable functional mode as claimed in claim 2, wherein the second step specifically comprises:
step 2.1, the processor initiates an instruction corresponding to the memory mapping register through writing the running information, and when the instruction is executed, the DMA controller judges whether the DMA controller is in a configuration mode, namely, the existing numerical value of the configuration execution state register is checked, and if the numerical value is 0, the memory access and writing are fed back to be successful; if the numerical value is 1, the DMA controller feeds back the failure of access and memory writing to the processor;
step 2.2, if the feedback access and memory writing is successful, the processor writes 1 into the data valid state register, the DMA controller enters mode judgment, pulls down the completion state register, writes 0 into the error state register, and activates the comparison module;
step 2.3, after the mode judgment is entered, the DMA controller checks that the initial address of the corresponding memory of the peripheral or the initial address of the target memory is 0, then the DMA controller enters the carrying mode judgment and writes 0 into the mode judgment register; otherwise, the execution mode judgment is performed, and 1 is written into the mode judgment register.
4. The method according to claim 3, wherein the entering of the transport mode is specifically:
the comparison module judges the following conditions: checking all values of the transport mode register, if any value is 0, sending an interrupt to the processor by the DMA controller, changing an error state register into 1, and finishing the pull-up of the state register; after the judgment is passed, comparing the initial address of the memory of the system memory in the transport mode with the initial address of the system memory, wherein the initial address of the memory of the system memory is less than or equal to the initial address of the memory of the system memory; then, calculating the sum of the initial address and the initial data size of the system memory by using an adder, and calculating the tail address of the memory of the system memory in the transport mode, wherein the former address is less than or equal to the latter address; when any condition is not met, the DMA controller sends an interrupt to the processor, changes the error state register to 2 and completes the pull-up of the state register; and if the conditions are met, checking the initial data size register, if the numerical value is 0, sending an interrupt to the processor by the DMA controller, changing the error state register into 4, and pulling up the state register.
5. The method according to claim 3, wherein the determining of the entry execution mode specifically comprises:
the comparison module makes the following determinations: checking the values of all execution mode registers, if at least one value of all types is 0, sending an interrupt to a processor by the DMA controller, changing an error state register into 1, and pulling up the state register; the starting address of the memory corresponding to the peripheral is sequentially matched with the starting address of the memory corresponding to the peripheral in the execution mode, if the address cannot be matched with any configuration address, the DMA controller sends an interrupt to the processor, the error state register is changed into 3, and the state register is pulled up; if the matching is successful, if the matching success type is 1, writing 1 into the matching type register, wherein the related information in the following steps corresponds to the type 1; then checking registers of the initial data size and the target data size, if any numerical value is 0, the DMA controller sends an interrupt to the processor, the error state register is changed to 4, and the state register is pulled up; and if the judgment is passed, checking whether the system memory address meets the preset configuration range.
6. The method for operating a DMA controller with configurable functional modes as claimed in claim 1, wherein the third step specifically comprises: if the DMA controller enters the carrying mode, the DMA controller determines data input by reading a data transmission direction register, namely: if the state is 0, transmitting the peripheral to the memory; if the state is 1, the memory is transmitted to the external device, the initial address of the memory is written into the current address register of the memory, and the initial data size is written into the memory and the residual data size register of the external device.
7. The method of claim 6, wherein if the external device is in a state of transferring to the memory, the external interface data is valid and the FIFO is not full, the data is written into the FIFO buffer, the size of the remaining data in the external device is updated, and the tail data in the buffer is sequentially written into the memory with the current memory address as the target when the FIFO is not empty, the DMA controller sends a ready signal to the external interface when the FIFO is not full, meanwhile, when the memory feedback is successfully written, the corresponding data is cleared from the FIFO, the current memory address and the size of the remaining data in the memory are updated, and meanwhile, whether the size of the remaining data is 0 is determined, if not, the above process is repeated; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller restores the idle state.
8. The method of claim 6, wherein if the DMA controller is in a state of transferring from the memory to the peripheral device, when the FIFO is not full, a read request is issued to the memory targeting the current memory address, if the read request is successful, the acquired data is written into the FIFO, and the current memory address and the size of the remaining data in the memory are updated, and at the same time, it is determined whether the size of the remaining data is 0, if not, the above process is repeated; otherwise, stopping data reading; meanwhile, when the FIFO is not fully empty and the peripheral interface receives a ready signal, the tail end data is cleared out of the FIFO, written into the peripheral interface and pulled up the interface valid signal, and the size of the peripheral residual data is updated and whether the size is 0 or not is judged, if not, the process is repeated; otherwise, the DMA controller sends an interrupt to the processor, the completion status register is pulled up, all the address memory mapping registers except the configuration information are cleared, and the DMA controller restores the idle state.
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| CN114968863A (en) * | 2022-05-26 | 2022-08-30 | 无锡华大国奇科技有限公司 | Data transmission method based on DMA controller |
| CN114996205B (en) * | 2022-07-21 | 2022-12-06 | 之江实验室 | On-chip data scheduling controller and method for auxiliary 3D architecture near memory computing system |
| CN116360853B (en) * | 2022-12-30 | 2023-12-12 | 中科驭数（北京）科技有限公司 | Register mapping method, device, equipment and medium |
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