CN116360853B - Register mapping method, device, equipment and medium - Google Patents
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- CN116360853B CN116360853B CN202211739087.5A CN202211739087A CN116360853B CN 116360853 B CN116360853 B CN 116360853B CN 202211739087 A CN202211739087 A CN 202211739087A CN 116360853 B CN116360853 B CN 116360853B
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- 238000004590 computer program Methods 0.000 claims description 6
- 238000012544 monitoring process Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present disclosure relates to a register mapping method, apparatus, device, and medium. The register mapping method comprises the following steps: generating a mapping instruction in response to an operation instruction aiming at the first register, wherein the mapping instruction comprises address information of the first register, operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction; determining address information of a target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register; according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register, the first register and the target memory space of the peripheral equipment are mapped, and according to the embodiment of the disclosure, the real-time mapping of the first register and the target memory space of the peripheral equipment can be realized.
Description
Technical Field
The disclosure relates to the field of computer technology, and in particular, to a register mapping method, device, equipment and medium.
Background
PCI (Peripheral Component Interconnect) is a standard for defining local buses, mainly a bus technology for connecting peripherals in computing systems, introduced by Intel (Intel) corporation in 1991. Such as a connection network card, a video card, a hard disk, etc., are commonly used in computer systems. Over decades, PCI family lineages have grown richer today and PCI connected devices are increasingly heterogeneous, such as the recently emerging data processing devices (Data Processing Unit, DPU devices) are also in use.
Like DPU devices, they have their own independent general-purpose CPU, memory, and peripherals, and these devices run an independent general-purpose operating System (commonly known as Linux), which runs completely isolated from the Host operating System, and the Host-side System (including the operating System) and the PCI-side device System (PCI Device System, including the operating System) can communicate through dedicated hardware logic circuits or networks, however, how to implement real-time mapping between Host-side registers and the memory space of the PCI-side device System is a technical problem that needs to be solved.
Disclosure of Invention
In order to solve the technical problems, the present disclosure provides a register mapping method, device, equipment and medium.
A first aspect of an embodiment of the present disclosure provides a register mapping method, including:
generating a mapping instruction in response to an operation instruction aiming at the first register, wherein the mapping instruction comprises address information of the first register, operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction;
determining address information of a target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register;
and mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
A second aspect of an embodiment of the present disclosure provides a register mapping apparatus, including:
the instruction generation module is used for responding to the operation instruction aiming at the first register and generating a mapping instruction, wherein the mapping instruction comprises address information of the first register, the operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction;
the address determining module is used for determining the address information of the target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register;
the register mapping module is used for mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
A third aspect of the disclosed embodiments provides an electronic device, comprising:
a processor;
a memory for storing executable instructions;
the processor is configured to read the executable instruction from the memory, and execute the executable instruction to implement the register mapping method provided in the first aspect.
A fourth aspect of embodiments of the present disclosure provides a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to implement the register mapping method provided in the first aspect above.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
the register mapping method, device, equipment and medium provided by the embodiment of the disclosure can respond to the operation instruction aiming at the first register to generate the mapping instruction, wherein the mapping instruction comprises address information of the first register, the operation type of the operation instruction and address information of the second register, the second register is used for storing data aiming at the operation instruction, the address information of a target memory space of the peripheral equipment corresponding to the first register is determined according to the address information of the first register, and the first register and the target memory space of the peripheral equipment are mapped according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register, so that the real-time mapping of the first register and the target memory space of the peripheral equipment is realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a register mapping method provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of mapping a first register to a target memory space of a peripheral device according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another mapping between a first register and a target memory space of a peripheral device according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a register mapping apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.
In order to solve the problem of real-time mapping between a host side register and a memory space of a peripheral device system, embodiments of the present disclosure provide a register mapping method, which is described below with reference to specific embodiments.
Fig. 1 is a flowchart of a register mapping method provided in an embodiment of the present disclosure, where the method may be performed by a register mapping apparatus, which may be implemented in software and/or hardware, and the register mapping apparatus may be configured in an electronic device, for example, a peripheral device connected to or communicating with a host system, a PCI device, and the like, where the PCI device may be any device connected to the host system through a PCI bus, such as a hard disk, a graphics card, and the like, and is not limited herein.
Fig. 2 is a schematic diagram of a target memory space mapping between a first register and a peripheral device according to an embodiment of the present disclosure, where the mapping includes a host system 21 and a peripheral device 20, and the peripheral device 20 includes a peripheral device register 22, a dedicated hardware logic circuit 23, and a peripheral device system 24.
The peripheral device register 22 is understood to be an interface for mapping between the host system 21 and the peripheral device 20, and the dedicated hardware logic 23 is used for communication between the host system 21 and the peripheral device 20, where the peripheral device system 24 includes a memory space 24-1, and a target memory space may be applied from the memory space 24-1 in advance, and the target memory space is used for mapping with the peripheral device register 22 in real time. The register mapping method provided by the embodiment of the present disclosure may be applied to fig. 2.
As shown in fig. 1, the register mapping method provided by the embodiment of the present disclosure includes the following steps.
S110, responding to an operation instruction aiming at a first register, generating a mapping instruction, wherein the mapping instruction comprises address information of the first register, operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction.
In the embodiment of the disclosure, when an operation instruction occurs in a first register, an electronic device generates a mapping instruction in response to the operation instruction for the first register, where the mapping instruction includes address information of the first register, an operation type of the operation instruction, and address information of a second register, and the second register is used for storing data for the operation instruction.
Alternatively, the operation type of the operation instruction may include a read operation, a write operation, a clear operation, and the like.
Alternatively, the data for the operation instruction may correspond to different data according to the difference of the operation instruction.
S120, according to the address information of the first register, determining the address information of a target memory space of the peripheral equipment corresponding to the first register.
In the embodiment of the disclosure, after generating a mapping instruction, the electronic device parses address information of a first register from the mapping instruction in response to the mapping instruction, and determines address information of a target memory space of the peripheral device corresponding to the first register according to the address information of the first register.
Optionally, a corresponding relationship exists between the first register and the target memory space of the peripheral device, and the electronic device can locate the position of the target memory space of the peripheral device according to the address information of the first register, so as to obtain the address information of the target memory space of the peripheral device.
Optionally, the correspondence between the first register and the target memory space of the peripheral device may be preset.
In the embodiment of the present disclosure, the storage size of the first register and the storage size of the target memory space of the peripheral device may be the same.
S130, mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
In the embodiment of the disclosure, after determining the address information of the target memory space of the peripheral device, the electronic device maps the first register and the target memory space of the peripheral device according to the address information of the target memory space of the peripheral device, the operation type of the operation instruction, and the address information of the second register.
Optionally, according to the difference of operation types of the operation instructions, the operations of mapping the first register and the target memory space of the peripheral device are also different.
In the embodiment of the disclosure, a mapping instruction can be generated in response to an operation instruction for a first register, where the mapping instruction includes address information of the first register, an operation type of the operation instruction, and address information of a second register, and the second register is used to store data for which the operation instruction is directed, determine address information of a target memory space of a peripheral device corresponding to the first register according to the address information of the first register, and map the first register and the target memory space of the peripheral device according to the address information of the target memory space of the peripheral device, the operation type of the operation instruction, and the address information of the second register, thereby implementing real-time mapping between the first register and the target memory space of the peripheral device.
On the basis of the above embodiment of the present disclosure, when the operation type is a read operation, S130 may specifically include: reading target read data in the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment; storing target read data into the second register according to the address information of the second register; the target read data stored in the second register is mapped to the first register.
In the embodiment of the present disclosure, the read operation refers to a corresponding operation that the host system is to read the target memory space address of the peripheral device.
The target read data is the data for which the read operation is directed.
Specifically, when the operation type of the operation instruction in the read-to-map instruction is a read operation, the electronic device reads target read data corresponding to the operation instruction of the first register from the target memory space of the peripheral device according to address information of the target memory space of the peripheral device, stores the read target read data into the second register according to address information of the second register, and maps the target read data in the second register to the first register in response to the target read data stored in the second register.
On the basis of the above embodiment of the present disclosure, when the operation type is a write operation, S130 may specifically include: reading target write data in the second register according to the address information of the second register; and storing the target write data into the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment.
In the disclosed embodiments, a write operation refers to a corresponding operation by which the host system writes new data.
The target write data is the data for which the write operation is directed.
Specifically, when the operation type of the operation instruction in the read-to-map instruction is write operation, the electronic device reads target write data in the second register according to the address information of the second register, and after the target write data is read, the electronic device stores the target write data in the second register according to the address information of the target memory space of the peripheral device, so that the mapping between the first register and the target memory space of the peripheral device is realized.
In an embodiment of the present disclosure, before reading the target write data in the second register according to the address information of the second register, the register mapping method further includes: and acquiring target write data corresponding to the write operation, and storing the target write data into a second register.
Specifically, when the operation type of the operation instruction responding to the first register is write operation, the electronic device acquires target write data corresponding to the write operation, and stores the target write data into the second register, so that the target write data can be directly read from the second register, and the mapping speed of the register is further improved.
In an embodiment of the present disclosure, after S110, that is, after generating the mapping instruction, the register mapping method may further include: and placing the mapping instruction into a mapping channel corresponding to the mapping instruction, wherein the mapping channel comprises an instruction register and a second register, and the instruction register is used for storing the mapping instruction.
Alternatively, there may be at least one instruction register within the mapping channel, i.e. the data of the instruction register may be one or more, while the instruction register within the mapping channel is in one-to-one correspondence with the second register.
Specifically, after generating a mapping instruction, the electronic device determines the idle state of the mapping channel, when the mapping channel in the idle state exists, selects one mapping channel from the mapping channels in the idle state as the mapping channel corresponding to the mapping instruction, places the mapping instruction into the mapping channel, when the mapping channel in the idle state does not exist, enters a waiting state, and places the mapping instruction into the mapping channel when the mapping channel in the idle state exists.
Further, the mapping channel includes instruction registers, which are constructed as lock-free queues, ensuring that the mapped instructions are first-in first-out and they are ring-shaped, i.e. the last element of the head of the queue is the tail of the queue.
Illustratively, when there is an idle state mapping channel, the queue tail pointer is incremented. And if the mapping channel is in the mapping channel without the idle state, namely, when the queue is full, waiting for the mapping channel in the idle state.
In some embodiments of the present disclosure, when multiple mapping instructions are generated simultaneously, multiple mapping instructions may be deposited into the same mapping channel when the number of instruction registers and second registers in the mapping channel satisfy the deposit requirements of the multiple mapping instructions.
In the embodiment of the disclosure, the mapping instructions are placed in the mapping channels corresponding to the mapping instructions, so that when a plurality of mapping instructions exist, the mapping instructions are ensured not to be missed, and meanwhile, the mapping instructions in the mapping channels can be read and executed according to the first-in first-out principle according to the sequence of placing the mapping instructions in the mapping channels.
In an embodiment of the present disclosure, the register mapping method further includes monitoring whether a mapping channel has a new mapping instruction in real time, and mapping a target memory space of the first register and the peripheral device in response to the new mapping instruction when the new mapping instruction is monitored.
In some embodiments of the present disclosure, the electronic device may monitor whether a mapping channel has a new mapping instruction in real time, and when it is monitored that a new mapping instruction is input, read and respond to the new mapping instruction, and implement real-time mapping between the first register and the target memory space of the peripheral device according to the new mapping instruction.
In other embodiments of the present disclosure, when a new mapping instruction exists in the mapping channel, the electronic device receives a notification that the new mapping instruction is placed, reads the new mapping instruction in response to the notification, and executes the new mapping instruction, so as to implement real-time mapping between the first register and the target memory space of the peripheral device.
In the embodiment of the disclosure, the electronic device can monitor whether a new mapping instruction exists in real time, so that the mapping instruction can be processed in time when the new mapping instruction exists, and real-time mapping of the first register and the target memory space of the peripheral device is ensured.
In the following, a specific example is described in detail for a mapping method of a first register and a target memory space of a peripheral device, and fig. 3 is another mapping schematic diagram of the first register and the target memory space of the peripheral device provided in this embodiment of the present disclosure, and as shown in fig. 3, the schematic diagram mainly includes a host system 31, a peripheral device mapping circuit 32, and a peripheral device system 30, where the peripheral device mapping circuit 32 includes a first register, a mapping instruction generator 33, and an intermediate register, the peripheral device system 30 includes a mapping instruction processor 34 and a memory 35, the memory 35 includes a target memory space of the peripheral device, the mapping instruction generator 33 is configured to generate a mapping instruction in response to an operation instruction for the first register, and the mapping instruction processor 34 is configured to read and execute the mapping instruction, and may specifically include determining address information of the target memory space of the peripheral device corresponding to the first register according to address information of the first register, and mapping the target memory space of the peripheral device according to address information of the peripheral device, an operation instruction type, and address information of the second register.
The first register in fig. 3 corresponds to the peripheral device register 22 in fig. 2, the mapping instruction generator 33 corresponds to the dedicated hardware logic circuit 23 in fig. 2, and the target memory space of the peripheral device belongs to a part of the memory space selected in advance from the memory space 24-1 in fig. 2.
Further, the intermediate side register includes an instruction register, a second register and a configuration register, the instruction register is used for storing a mapping instruction, the second register is used for storing data aimed by an operation instruction, the configuration register is used for storing configuration information of the intermediate side register, and at least one instruction register and at least one second register form a mapping channel, that is, the intermediate side register includes at least one mapping channel.
Alternatively, the configuration information of the intermediate side registers may include information of the size, type, number of mapping channels, and the like of each register.
Optionally, the number of mapping channels is determined according to the configuration of the specific intermediate side register.
Specifically, the mapping instruction generator 33 may select one mapping channel in advance, the mapping instruction generator 33 obtains the operation type of the operation instruction, the address information of the first register, and the address information of the second register in the mapping channel in response to the operation instruction for the first register, generates the mapping instruction according to the operation type of the operation instruction, the address information of the first register, and the address information of the second register in the mapping channel, and simultaneously places the mapping instruction in the instruction register of the mapping channel, and when the operation type is a write operation, obtains the target write data at the same time, and stores the target write data in the second register of the mapping channel.
The mapping instruction processor 34 monitors the mapping channel in real time, reads the mapping instruction from the instruction register of the mapping channel when the mapping instruction is detected to be put into the mapping channel, determines the address information of the target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register in the mapping instruction, and further maps the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
It should be noted that, the specific implementation method for mapping the first register and the target memory space of the peripheral device according to the address information of the target memory space of the peripheral device, the operation type of the operation instruction, and the address information of the second register is similar to the specific real-time manner in the above embodiment of the present disclosure, and will not be described herein.
In the embodiment of the disclosure, the mapping instruction can be generated by the mapping instruction generator, and the mapping instruction processor reads and executes the mapping instruction, so that the real-time mapping of the first register and the target memory space of the peripheral equipment is realized, and meanwhile, the expansion of the mapping instruction can be realized by setting different operation types, so that the coupling between the mapping instruction generator and the mapping instruction processor is reduced, and the data processing pressure of the host system can be relieved by the real-time mapping of the first register and the target memory space of the peripheral equipment.
Fig. 4 is a schematic structural diagram of a register mapping apparatus according to an embodiment of the present disclosure.
In the embodiment of the disclosure, the register mapping device may be disposed in an electronic device, which is understood as a part of functional modules in the electronic device. Specifically, the electronic device may be a peripheral device connected to or communicating with the host system, a PCI device, or the like, where the PCI device may be any device connected to the host system through a PCI bus, such as a hard disk, a graphics card, or the like, and is not limited herein.
As shown in fig. 4, the register mapping apparatus 400 may include an instruction generation module 410, an address determination module 420, and a register mapping module 430.
The instruction generation module 410 may be configured to generate, in response to an operation instruction for a first register, a mapping instruction, where the mapping instruction includes address information of the first register, an operation type of the operation instruction, and address information of a second register, where the second register is configured to store data for which the operation instruction is directed.
The address determining module 420 may be configured to determine address information of a target memory space of the peripheral device corresponding to the first register according to the address information of the first register.
The register mapping module 430 may be configured to map the first register and the target memory space of the peripheral device according to address information of the target memory space of the peripheral device, an operation type of the operation instruction, and address information of the second register.
In the embodiment of the disclosure, a mapping instruction can be generated in response to an operation instruction for a first register, where the mapping instruction includes address information of the first register, an operation type of the operation instruction, and address information of a second register, and the second register is used to store data for which the operation instruction is directed, determine address information of a target memory space of a peripheral device corresponding to the first register according to the address information of the first register, and map the first register and the target memory space of the peripheral device according to the address information of the target memory space of the peripheral device, the operation type of the operation instruction, and the address information of the second register, thereby implementing real-time mapping between the first register and the target memory space of the peripheral device.
In some embodiments of the present disclosure, the type of operation is a read operation.
The register mapping module 430 may include a first data reading unit 4301, a first data storing unit 4302, and a register mapping unit 4303, among others.
The first data reading unit 4301 may be configured to read target read data in a target memory space of a peripheral device according to address information of the target memory space of the peripheral device.
The first data storing unit 4302 may be configured to store target read data in the second register according to address information of the second register.
The register mapping unit 4303 may be used to map target read data stored in the second register to the first register.
In some embodiments of the present disclosure, the type of operation is a write operation.
The register mapping module 430 may further include a second data reading unit 4304 and a second data storing unit 4305, among others.
The second data reading unit 4304 may be configured to read target write data in the second register according to address information of the second register.
The second data storing unit 4305 may be configured to store the target write data into the target memory space of the peripheral device according to address information of the target memory space of the peripheral device.
In some embodiments of the present disclosure, the register mapping module 430 may further include a third data store unit 4306.
The third data storing unit 4306 may be configured to obtain target write data corresponding to the write operation, and store the target write data in the second register.
In some embodiments of the present disclosure, the register map 400 may further include an instruction deposit module 440.
The instruction depositing module 440 may be configured to, after generating the mapping instruction, place the mapping instruction into a mapping channel corresponding to the mapping instruction, where the mapping channel includes an instruction register and a second register, and the instruction register is configured to deposit the mapping instruction.
In some embodiments of the present disclosure, the register map 400 may further include an instruction monitor module 450.
The instruction monitoring module 450 may be configured to monitor whether a new mapping instruction exists in the mapping channel in real time, and when the new mapping instruction is detected, map the target memory space of the first register and the peripheral device in response to the new mapping instruction.
It should be noted that, the register mapping apparatus 400 shown in fig. 4 may perform the steps in the above method embodiments, and implement the processes and effects in the above method embodiments, which are not described herein.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
In the embodiment of the present disclosure, the electronic device shown in fig. 5 may be a peripheral device, a PCI device, etc. connected to or communicating with the host system, where the PCI device may be any device connected to the host system through a PCI bus, such as a hard disk, a graphics card, etc., which is not limited herein.
As shown in fig. 5, the electronic device may include a processor 510 and a memory 520 storing computer program instructions.
In particular, the processor 510 described above may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or may be configured as one or more integrated circuits that implement embodiments of the present disclosure.
Memory 520 may include mass storage for information or instructions. By way of example, and not limitation, memory 520 may comprise a Hard Disk Drive (HDD), floppy Disk Drive, flash memory, optical Disk, magneto-optical Disk, magnetic tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of these. Memory 520 may include removable or non-removable (or fixed) media, where appropriate. The memory 520 may be internal or external to the integrated gateway device, where appropriate. In a particular embodiment, the memory 520 is a non-volatile solid state memory. In a particular embodiment, the Memory 520 includes Read-Only Memory (ROM). The ROM may be mask-programmed ROM, programmable ROM (PROM), erasable PROM (Electrical Programmable ROM, EPROM), electrically erasable PROM (Electrically Erasable Programmable ROM, EEPROM), electrically rewritable ROM (Electrically Alterable ROM, EAROM), or flash memory, or a combination of two or more of these, where appropriate.
Processor 510 reads and executes computer program instructions stored in memory 520 to perform the steps of the register mapping method provided by embodiments of the present disclosure.
In one example, the electronic device may also include a transceiver 530 and a bus 540. Wherein, as shown in fig. 5, the processor 510, the memory 520 and the transceiver 530 are connected and communicate with each other through a bus 540.
Bus 540 includes hardware, software, or both. By way of example, and not limitation, the buses may include an accelerated graphics port (Accelerated Graphics Port, AGP) or other graphics BUS, an enhanced industry standard architecture (Extended Industry Standard Architecture, EISA) BUS, a Front Side BUS (FSB), a HyperTransport (HT) interconnect, an industry standard architecture (Industrial Standard Architecture, ISA) BUS, an InfiniBand interconnect, a Low Pin Count (LPC) BUS, a memory BUS, a micro channel architecture (Micro Channel Architecture, MCa) BUS, a peripheral control interconnect (Peripheral Component Interconnect, PCI) BUS, a PCI-Express (PCI-X) BUS, a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) BUS, a video electronics standards association local (Video Electronics Standards Association Local Bus, VLB) BUS, or other suitable BUS, or a combination of two or more of these. Bus 540 may include one or more buses, where appropriate.
The present disclosure also provides a computer-readable storage medium, which may store a computer program that, when executed by a processor, causes the processor to implement the register mapping method provided by the embodiments of the present disclosure.
The storage medium may, for example, include a memory 520 of computer program instructions executable by the processor 510 of the electronic device to perform the register mapping methods provided by embodiments of the present disclosure. Alternatively, the storage medium may be a non-transitory computer readable storage medium, for example, a ROM, a random access memory (Random Access Memory, RAM), a Compact Disc ROM (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A register mapping method, comprising:
generating a mapping instruction in response to an operation instruction aiming at a first register, wherein the mapping instruction comprises address information of the first register, an operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction;
determining address information of a target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register;
and mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
2. The method of claim 1, wherein the type of operation is a read operation;
mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register, wherein the mapping comprises the following steps:
reading target read data in the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment;
storing the target read data into the second register according to the address information of the second register;
the target read data stored in the second register is mapped to the first register.
3. The method of claim 1, wherein the type of operation is a write operation;
mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register, wherein the mapping comprises the following steps:
reading target write data in the second register according to the address information of the second register;
and storing the target write data into the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment.
4. A method according to claim 3, wherein prior to said reading the target write data in the second register in accordance with the address information of the second register, the method further comprises:
and acquiring target write data corresponding to the write operation, and storing the target write data into the second register.
5. The method of claim 1, wherein after the generating the mapping instruction, the method further comprises:
and placing the mapping instruction into a mapping channel corresponding to the mapping instruction, wherein the mapping channel comprises an instruction register and a second register, and the instruction register is used for storing the mapping instruction.
6. The method of claim 5, wherein the method further comprises:
and monitoring whether a new mapping instruction exists in the mapping channel in real time, and mapping the first register and the target memory space of the peripheral equipment in response to the new mapping instruction when the new mapping instruction exists.
7. A register mapping apparatus, comprising:
the instruction generation module is used for responding to an operation instruction aiming at a first register and generating a mapping instruction, wherein the mapping instruction comprises address information of the first register, an operation type of the operation instruction and address information of a second register, and the second register is used for storing data aiming at the operation instruction;
the address determining module is used for determining the address information of the target memory space of the peripheral equipment corresponding to the first register according to the address information of the first register;
and the register mapping module is used for mapping the first register and the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment, the operation type of the operation instruction and the address information of the second register.
8. The apparatus of claim 7, wherein the type of operation is a read operation;
the register mapping module comprises a first data reading unit, a first data storing unit and a register mapping unit;
the first data reading unit is used for reading target read data in the target memory space of the peripheral equipment according to the address information of the target memory space of the peripheral equipment;
the first data storing unit is used for storing the target read data into the second register according to the address information of the second register;
the register mapping unit is configured to map the target read data stored in the second register to the first register.
9. An electronic device, comprising:
a processor;
a memory for storing executable instructions;
wherein the processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the register mapping method of any of the preceding claims 1-6.
10. A computer readable storage medium, characterized in that the storage medium stores a computer program, which when executed by a processor causes the processor to implement the register mapping method of any of the preceding claims 1-6.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538710A (en) * | 2003-02-26 | 2004-10-20 | Multiple registers | |
| CN102646074A (en) * | 2012-02-22 | 2012-08-22 | 中国人民解放军国防科学技术大学 | Address mapping method for large memory devices of Loongson 3A platforms |
| CN106209121A (en) * | 2016-07-15 | 2016-12-07 | 中国科学院微电子研究所 | Multi-mode and multi-core communication baseband SoC chip |
| CN110750328A (en) * | 2019-09-23 | 2020-02-04 | 东软集团股份有限公司 | Equipment access method and device and terminal equipment |
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN114115996A (en) * | 2020-08-28 | 2022-03-01 | 瞻博网络公司 | Mapped register access by microcontroller |
| CN114153779A (en) * | 2021-10-31 | 2022-03-08 | 郑州云海信息技术有限公司 | I2C communication method, system, equipment and storage medium |
| CN114328322A (en) * | 2022-03-17 | 2022-04-12 | 之江实验室 | DMA controller operation method capable of configuring function mode |
| CN114610557A (en) * | 2022-05-11 | 2022-06-10 | 宏晶微电子科技股份有限公司 | Method and device for testing equipment driving unit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9792245B2 (en) * | 2014-12-09 | 2017-10-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Peripheral component interconnect express (PCIe) devices with efficient memory mapping by remapping a plurality of base address registers (BARs) |
| US10248468B2 (en) * | 2016-01-11 | 2019-04-02 | International Business Machines Corporation | Using hypervisor for PCI device memory mapping |
-
2022
- 2022-12-30 CN CN202211739087.5A patent/CN116360853B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538710A (en) * | 2003-02-26 | 2004-10-20 | Multiple registers | |
| CN102646074A (en) * | 2012-02-22 | 2012-08-22 | 中国人民解放军国防科学技术大学 | Address mapping method for large memory devices of Loongson 3A platforms |
| CN106209121A (en) * | 2016-07-15 | 2016-12-07 | 中国科学院微电子研究所 | Multi-mode and multi-core communication baseband SoC chip |
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN110750328A (en) * | 2019-09-23 | 2020-02-04 | 东软集团股份有限公司 | Equipment access method and device and terminal equipment |
| CN114115996A (en) * | 2020-08-28 | 2022-03-01 | 瞻博网络公司 | Mapped register access by microcontroller |
| CN114153779A (en) * | 2021-10-31 | 2022-03-08 | 郑州云海信息技术有限公司 | I2C communication method, system, equipment and storage medium |
| CN114328322A (en) * | 2022-03-17 | 2022-04-12 | 之江实验室 | DMA controller operation method capable of configuring function mode |
| CN114610557A (en) * | 2022-05-11 | 2022-06-10 | 宏晶微电子科技股份有限公司 | Method and device for testing equipment driving unit |
Non-Patent Citations (1)
| Title |
|---|
| 黄璜 ; 田伟.基于CPLD的TMS320C6727B外设重叠地址空间解析方法的研究与实现.《海军航空工程学院学报》.2014,196-200. * |
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