CN114968863A - Data transmission method based on DMA controller - Google Patents
Data transmission method based on DMA controller Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a data transmission method based on a DMA controller, which relates to the field of data transmission and comprises the following steps: responding to a data transmission request initiated by a peripheral device received by a DMA controller, and carrying data in a peripheral cache to a memory through a bus or carrying data in the memory to the peripheral cache; responding to the DMA controller to complete data handling based on the data transmission request, and directly sending a response signal to the peripheral equipment; and responding to the DMA controller to finish n rounds of data transmission, and sending a DMA interrupt request to the CPU after finishing the transmission task set by the CPU, so that the CPU can respond to the DMA interrupt request and execute ending work conveniently. The scheme sets the handshake signals between the peripheral and the DMA controller, does not need the CPU to receive and respond the peripheral interrupt request and execute ending work in each turn, can obviously reduce the times of CPU response interrupt, greatly reduces the burden of the CPU and improves the execution efficiency of operation.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a data transmission method for a controller.
Background
In the field of integrated circuits, a CPU performs data transmission by receiving an interrupt request of a peripheral Buffer, and reads data in the peripheral to a memory through a bus, or carries the memory to the Buffer, but the CPU stops a running process when responding to an interrupt, and the CPU needs to frequently respond in the process of transmitting a large amount of data, which affects the execution efficiency of the CPU.
In the related art, the DMA controller is arranged to take over the execution operation of the CPU, and the CPU is interrupted during the data transmission ending process in each Buffer, so that the CPU only needs to respond to an interrupt request without transmitting data, thereby reducing the load of the CPU. However, in this way, each interrupt request of the Buffer requires a CPU to respond, and the execution efficiency of the CPU cannot be further improved.
Disclosure of Invention
The application provides a data transmission method based on a DMA controller, which solves the problems that a CPU (central processing unit) frequently responds to interrupt requests and has low execution efficiency in the prior art. Specifically, the method comprises the following steps:
the CPU sends an instruction to a peripheral and the DMA controller and sets a transmission task;
responding to a data transmission request initiated by the peripheral equipment received by the DMA controller, and transporting data in a peripheral cache Buffer to a memory through a bus, or transporting the data in the memory to the peripheral cache; the data transmission request is initiated when the peripheral cache meets data transmission conditions;
responding to the DMA controller to finish data transportation based on the data transmission request, directly sending a response signal to the peripheral equipment, and waiting for the next round of data transmission request; the response signal is used for indicating the DMA controller to complete the data transmission of the current round;
responding to the DMA controller to finish n rounds of data transmission, and sending a DMA interrupt request to the CPU after finishing the transmission task set by the CPU, so that the CPU can respond to the DMA interrupt request and execute ending work conveniently; wherein n is the number of rounds required for completing data transmission between the peripheral and the memory, and n is a positive integer.
The beneficial effect that technical scheme that this application provided brought includes at least: setting handshake signals between the peripheral and the DMA controller in advance; when data transmission is carried out, the DMA controller directly executes n rounds of data transmission operation according to the data transmission request; after the DMA controller determines to complete the complete data transmission operation according to the preset setting of the CPU, the DMA controller sends a DMA interrupt request to the CPU, so that the CPU responds to the interrupt request to complete the ending work. Compared with the working mode that each round of the CPU receives the peripheral interrupt, sets the DMA controller and responds to the ending of the DMA interrupt, the frequency of the CPU responding to the interrupt can be reduced, the load of the CPU is reduced, and the execution efficiency of the parallel operation of the CPU is improved.
Drawings
Fig. 1 is a block diagram showing a configuration of a computer apparatus for performing data transmission in the related art;
FIG. 2 is a flow chart illustrating data transmission performed by a computer device according to the related art;
FIG. 3 is a flow chart of a DMA controller based data transmission method provided by an embodiment of the present application;
FIG. 4 is a block diagram illustrating a data transmission method based on a DMA controller according to an embodiment of the present disclosure;
FIG. 5 is a flow chart of a DMA controller based data transfer method according to another embodiment of the present application;
FIG. 6 shows a schematic diagram of the connection of handshake signals between a peripheral and a DMA controller;
FIG. 7 illustrates a handshake timing diagram between a peripheral cache and a DMA controller;
FIG. 8 is a flow chart diagram illustrating a DMA controller based data transfer method;
FIG. 9 is a diagram of handshake signal connections of a DMA and a controller and a peripheral device in the same clock domain according to an embodiment of the present application;
fig. 10 is a diagram of connections of handshake signals of a DMA and a controller and a peripheral located in different clock domains according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, the following detailed description of the embodiments of the present application will be made with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
A CPU: a Central Processing Unit (CPU) is one of the main devices of an electronic computer, and is a core accessory in the computer. Its functions are mainly to interpret computer instructions and to process data in computer software. The CPU is the core component of the computer responsible for reading, decoding and executing instructions. The CPU mainly comprises two parts, namely a controller and an arithmetic unit, and also comprises a cache memory and a bus for realizing data and control of the connection between the cache memory and the arithmetic unit. The three major core components of the computer are the CPU, the memory and the input/output device. The central processing unit mainly has the functions of processing instructions, executing operations, controlling time and processing data. The CPU in the scheme sets a transmission task for the peripheral and the DMA controller, receives and responds to the interrupt sent by the peripheral and the DMA controller, executes ending work and completes a data transmission task.
A DMA controller: direct Memory Access (DMA) controllers are an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on a large amount of interrupt load of the CPU, and are a data transfer method that can greatly reduce the workload of the CPU. The CPU has many functions such as data transfer, calculation, control program transfer, etc., but data transfer (especially, transfer of a large amount of data) may not require the CPU. For example, it is desirable that the data of the peripheral device is copied to the memory, and the data copying can be completed by providing a data path for the two modules and adding some components for controlling the transfer. The whole data transmission operation is carried out under the control of a DMA controller, a CPU carries out a little processing except when the data transmission is started and finished (peripheral equipment and the DMA controller are arranged at the beginning and interrupt processing is carried out at the end), and the CPU can continue other work in the transmission process. Therefore, in most of time, the CPU calculation and the I/O operation are in parallel operation, so that the efficiency of the whole computer system is greatly improved.
Fig. 1 is a block diagram showing a configuration of a computer apparatus for performing data transmission in the related art. The chip of the computer equipment comprises a CPU, a DMA controller, a peripheral and a memory, and the intercommunication connection is established through a bus. The peripheral is internally provided with a peripheral cache buffer and is connected with other chips (such as a FLASH memory chip and the like) outside the chip. Peripherals are devices that require data interaction with other devices, such as printers, storage devices, etc. When the peripheral needs to transmit data, a peripheral interrupt request is sent to the CPU. Similarly, the DMA controller needs to send a DMA interrupt request to the CPU after performing "data transfer". Taking the peripheral device accessing the memory data as an example, as shown in fig. 2, the process includes the following steps:
when the peripheral needs to execute specific operation and needs to perform a data transmission task with the memory, the CPU determines and sets the transmission task to the peripheral and the DMA controller, and starts to start the transmission task.
And secondly, sending peripheral interrupt to the CPU through the peripheral under the condition that the peripheral cache meets the data transmission.
And thirdly, after receiving the peripheral interrupt sent by the peripheral, the CPU determines that data needs to be read from the memory and stores the data into a peripheral cache (buffer), and then sends a scheduling instruction to the DMA controller to set the DMA controller.
And fourthly, after the DMA controller takes over the authority, the CPU does not supervise the operation process any more, but the DMA controller transfers the data in the memory to the buffer of the peripheral through the bus.
And fifthly, after the DMA controller transfers the data to the peripheral buffer, immediately sending a DMA interrupt to the CPU to indicate that one data transfer is finished, and the CPU is responsible for executing ending work.
Sixthly, because the data cannot be carried out at one time, n times of repeated operation needs to be executed subsequently, after the peripheral obtains the data (partial data), the peripheral continues to send peripheral interrupt to the CPU, the CPU continues to respond to the interrupt, and the DMA controller is set.
In a scenario where a large amount of data is written to the peripheral, the CPU needs to continuously repeat the above process of responding to the interrupt, and especially when the CPU executes a large amount of parallel processes, frequent switching increases workload of the CPU, reduces systematicness, and causes a phenomenon of stuttering or even system bursting.
Fig. 3 is a flowchart of a data transmission method based on a DMA controller according to an embodiment of the present application. The method comprises the following steps:
When the computer device needs to execute a data transfer task, the CPU first sets the transfer task by sending an instruction to the peripheral and the DMA controller based on the transfer task. When the peripheral determines that a transfer is possible, a data transfer request is sent to the DMA controller.
The peripheral is internally provided with a peripheral cache buffer, the data transmission request is initiated when the peripheral cache meets the data transmission condition, and the peripheral is connected with other chips, such as a flash chip, and is used for receiving data carried by the memory of the computer equipment or sending the stored data to the memory. In the scheme, before transmission, handshake signals between the peripheral and the DMA controller are set, and data transmission is carried out based on the handshake signals. When the DMA controller receives a data transmission request sent by the peripheral, the DMA controller determines the operation to be executed, and then the DMA controller carries the data in the peripheral cache inside the peripheral to the memory through the bus, or carries the data in the memory to the peripheral cache. Referring to fig. 4 specifically, the bus connects the buffer of the external device and the memory, and the DMA controller fetches data from the buffer and transfers the data to the memory through the bus, or writes the data in the memory into the buffer of the external device through the bus.
And 303, responding to the DMA controller to finish data transportation based on the data transmission request, and directly sending a response signal to the peripheral equipment.
Taking the case that the DMA controller writes data to the external device as an example, the DMA controller fetches a certain amount of data from the memory according to the data transmission request, and sends the data to the buffer of the external device through the bus, and then directly sends a response signal to the external device (a direct connection signal between the DMA and the external device, not through the bus). The purpose of the acknowledge signal is to inform the peripheral device to instruct the DMA controller to complete the data transfer of the current round (the data fetched from the memory has been transferred) and to wait for the next data transfer request. At this time, the peripheral does not acquire the complete data required by the transmission task, and needs to continue to receive multiple rounds of data transmission operations.
And step 304, responding to the fact that the DMA controller completes n rounds of data transmission, and sending a DMA interrupt request to the CPU after completing the transmission task set by the CPU, so that the CPU can respond to the DMA interrupt request and execute ending work conveniently.
Different from the related art, in the related art, after the DMA controller executes a transfer operation once, a DMA interrupt request needs to be sent to the CPU, while the amount of data to be transferred once is limited, n rounds of data transfer are needed to execute a complete transfer task, that is, n rounds of interrupts are needed in total to complete data transfer between the peripheral and the memory. However, in the present solution, the DMA controller omits this operation step, and continues to receive the data transmission request sent by the peripheral after each data transfer is completed, and indicates that the data transmission is completed when the transmission task amount set by the CPU is completed after all data transmissions are completed (n rounds of data transmission operations), and the DMA controller will send a DMA interrupt request to the CPU at this time, indicating that all operations have been completed, requesting the CPU to respond to the interrupt, and executing the finalization operation.
For the peripheral, when the transmission needs to be finished, a peripheral interrupt request needs to be sent to the CPU, and the CPU executes ending work when determining that the DMA interrupt request and the peripheral interrupt request are received. That is, the CPU participates in the ending stage of a complete transmission task, and the DMA controller takes over the transmission operation directly according to the data transmission instruction sent by the peripheral device in the rest of the time. The CPU has higher execution efficiency and less burden.
In summary, in the scheme provided in the embodiment of the present application, a handshake signal is set in advance between the peripheral and the DMA controller; when data transmission is carried out, the DMA controller directly executes n rounds of data transmission operation according to the data transmission request; after the DMA controller determines to complete the complete data transmission task according to the preset setting of the CPU, the DMA interrupt request is sent to the CPU, so that the CPU can respond to the interrupt request to complete the ending work conveniently. Compared with the working mode that each round of the CPU receives the peripheral interrupt, sets the DMA controller and responds to the ending of the DMA interrupt, the frequency of the CPU responding to the interrupt can be reduced, the load of the CPU is reduced, and the execution efficiency of the parallel operation of the CPU is improved.
Fig. 5 is a flowchart of a DMA controller-based data transfer method according to another embodiment of the present application. The method comprises the following steps:
step 501, setting handshake signals between the DMA controller and the peripheral, wherein different handshake signals are used for representing different data transmission directions and data transmission types; and when the external device meets the data transmission condition, generating a corresponding handshake signal and sending a data transmission request.
For the problem that the CPU frequently sets the DMA controller in the related technology, the scheme can set an execution strategy of data transmission in advance, and specifically, the execution strategy is determined through different handshaking signals, namely, when the peripheral equipment needs to execute a specific transmission operation, the peripheral equipment directly sends a data transmission request to the DMA controller according to the corresponding handshaking signals. The data transmission conditions of the peripheral cache in the peripheral are determined according to specific services. If the data is read from the external memory chip to the internal memory, the data can be triggered when the amount of the buffer cache exceeds a certain set threshold. If the data is written to the external memory chip, the data writing can be triggered when the data amount registered by the buffer is lower than a certain set threshold. In addition, before starting data transmission, the CPU needs to set a transmission task for the peripheral and the DMA controller, such as how much data to read from the peripheral or how much data to write to the peripheral, corresponding to n rounds of data transmission in the present scheme.
Step 502, the DMA controller determines a target handshake signal corresponding to the data transmission request, and matches the data transmission direction and the data transmission type to which the target handshake signal belongs.
And when receiving a data transmission signal sent by the peripheral equipment, the DMA controller determines a target handshake signal corresponding to the request and matches the data transmission direction and the data transmission type of the target handshake signal. The data transmission type specifies the size and other data attributes of data to be transmitted at a time, including read data signals and write data signals, and the corresponding data transmission directions respectively correspond to reading data in the peripheral and writing data into the peripheral.
The read data signals comprise a first read data signal rx _ single and a second read data signal rx _ burst, wherein the rx _ single signal indicates that the data volume read in each request is single data, and the rx _ burst signal indicates that the data volume read in each request is burst data; the bit width and length of burst are set by the CPU inside the DMA controller in advance. The write data signals include a first write data signal tx _ single and a second write data signal tx _ burst; the tx _ single signal indicates that the amount of data written per request is single data, and the tx _ burst signal indicates that the amount of data written per time is burst data. Specifically, as shown in fig. 6, fig. 6 shows a schematic diagram of the connection of handshake signals between the peripheral and the DMA controller.
In response to the target handshake signal corresponding to the read data signal, the DMA controller reads the data of the target data amount from the peripheral cache to the memory through the bus, step 503.
When the DMA controller determines that the target control signal is an rx _ single signal or an rx _ burst signal, extracting data with corresponding size from a buffer of the peripheral according to the data volume represented by the rx _ single signal or the rx _ burst signal, and then transmitting the data to the memory through the bus.
The first read reply signal rx _ single _ ack is a signal corresponding to the first read data signal rx _ single indicating that the DMA controller has successfully transferred a single data to the memory. The response signal is a signal directly transmitted to the peripheral device, and is not transmitted via the bus.
And step 505, after responding to the DMA controller to read the burst data from the peripheral cache into the memory, directly sending a second read response signal to the peripheral.
The second read reply signal rx _ burst _ ack is a signal corresponding to the second read data signal rx _ burst and indicates that the DMA controller has successfully transferred the burst data to the memory. The response signal is a signal directly transmitted to the peripheral device, and is not transmitted via the bus.
In step 506, in response to the target handshake signal corresponding to a write data signal, the DMA controller writes the data of the target data amount in the memory into the peripheral cache through the bus.
Similarly, when the computer device needs to transmit the memory data to the peripheral, the target handshake signal sent by the peripheral is the first write data signal tx _ single or the second write data tx _ burst. And after determining the write data signal, the DMA controller directly writes the data of the target data volume into the peripheral cache.
The first write acknowledge signal tx _ single _ ack is a signal corresponding to the tx _ single signal indicating that the DMA has successfully transferred a single data in the memory to the peripheral buffer via the bus.
The second write acknowledge signal tx _ burst _ ack is a signal corresponding to the tx _ burst signal, and indicates that the DMA has successfully transferred the burst data in the memory to the peripheral buffer via the bus. The burst width and the burst length of the burst data are specifically set by the CPU inside the DMA controller. For example, 64 bytes of data are to be transmitted, Burst width is set to 32 bits (i.e., 4 bytes), Burst length is set to 16, and 64 bytes of data can be transmitted in a Burst transmission.
Figure 7 shows a handshake timing diagram between a peripheral and a DMA controller. Firstly, indicating that the buffer meets the data transmission request, initiating a handshake signal corresponding to the data transmission request by the peripheral equipment, and keeping high level when the response signal is not received; indicating that the DMA controller receives a data transmission request and performs data transmission according to a specified data volume; thirdly, the DMA controller sends a response signal after finishing data transmission; fourthly, the peripheral equipment receives the response signal sent by the DMA controller, cancels the data transmission request and recovers the low level; indicating that DMA controller affirms the peripheral has cancelled the data transmission request and cancels the answer signal. At this point, both parties complete a hardware handshake.
And 509, responding to the DMA controller receiving the data transmission request sent by the peripheral again, continuing to perform data transportation and send response signal operation according to the data transmission request until n rounds of data transmission are completed.
When the peripheral meets the data transmission condition again, the data transmission request is initiated again, the DMA controller repeats the content of the steps, and the multi-round hardware handshake and data transmission steps are completed until the complete data is transmitted to the corresponding position.
Step 510, when the DMA controller completes n rounds of data transmission, a DMA interrupt request is sent to the CPU.
It should be noted that, after the last round of data transmission of the DMA controller is completed (n rounds of data), the DMA controller sends a DMA interrupt request to the CPU. Or, a handshake signal is additionally arranged between the peripheral and the DMA controller, and is used for the peripheral to send a data completion signal to the DMA controller, the signal is also a handshake signal which is set in advance, the DMA controller determines to complete all operations based on the handshake signal, and sends a DMA interrupt request to the CPU, which indicates that all operations are completed.
Step 511, when the CPU receives the peripheral interrupt and the DMA interrupt, the CPU responds to the DMA interrupt and the peripheral interrupt, and executes the ending work of the DMA controller and the peripheral side.
When the CPU receives the peripheral interrupt request, responding to the peripheral interrupt and executing the ending work of the peripheral side; when the CPU receives the DMA controller interrupt request, the DMA interrupt is responded and the ending work of the DMA side is executed. And when the CPU finishes the ending work of the peripheral side and the DMA controller side, the data transmission task is finished.
In summary, in the present solution, by setting the handshake signals between the peripheral and the DMA controller, when data transmission is required, the peripheral directly sends a target handshake signal to the DMA controller, and performs matching through the DMA to determine a corresponding data transmission direction and type, and then determines to transmit data in the memory to the peripheral buffer through the bus, or to transmit data in the buffer to the memory. And after the DMA controller transmits the target amount of data to a corresponding place, directly sending a response signal to the peripheral equipment according to the set handshake signal to inform the peripheral equipment of finishing hardware handshake. The peripheral device may then proceed to the next request and transfer operation. During the completion of the n-round data transfer process, the DMA does not have to send a DMA interrupt request, and the CPU may perform other processes. After the whole data transmission is finished, the CPU makes an interrupt response after receiving the peripheral interrupt and the DMA interrupt, and executes ending work. During the period, no matter how many times of transmission between the peripheral and the DMA controller is completed, the CPU does not need to participate. Thereby greatly reducing the burden of the CPU and improving the system performance.
Because the handshake signals between the peripheral and the DMA controller are direct connection signals, the delay is small, and the signal lines are set specifically according to actual conditions. The data transmission between the DMA controller and the peripheral needs to be completed through the bus, and in a large chip with a complex bus, the delay is large, so that it may happen that the DMA controller has sent all data and sent a response signal to complete the handshake with the peripheral, but still some data is on the way and does not reach the peripheral. If the peripheral device does not pay attention to the fact, the peripheral device may mistakenly think that the internal buffer has enough free space, and the transmission request can be sent out again, so that a logic function error is caused.
In order to avoid the problem, for the situation that the DMA controller writes data to the external device every time, the external device counts how much data is received, only the external device receives a response signal to complete the handshake with the DMA controller, and the actually received data reaches the data volume agreed by the handshake, and after the internal cache of the external device meets the requirement of sending data transmission again, the external device sends the requirement of writing data to the DMA controller again. As shown in fig. 8.
Fig. 8 is a flow chart illustrating a DMA controller based data transfer method. After the peripheral sends a data transmission request to the DMA controller, the DMA controller matches a target handshake signal, determines the data transmission direction and the data transmission type, and then transmits data between the buffer and the memory through the bus. And sending a response signal to the peripheral after the transmission is finished. After receiving the response signal, the peripheral does not directly enter the next period, but counts the received data to determine whether the target data amount corresponds to the response signal. When it is determined to be consistent, a data transfer request is sent again to the DMA controller. In this way, the CPU receives the interrupt request signal to complete the data transmission. And does not cause logic function errors.
The above aspects describe the operation mode in which the peripheral and the DMA controller are located in the same clock domain, that is, as shown in fig. 9, the peripheral directly sends a request signal (data transfer request) to the DMA controller; the corresponding DMA controller directly sends an acknowledgement signal (acknowledge signal) to the peripheral. However, when the peripheral and the DMA controller are in different clock domains, a synchronizer is further required to synchronize the handshake signals to the corresponding clock domains in order to avoid the meta-stability. As shown in fig. 10, a request signal sent by the peripheral device passes through the synchronizer, an acknowledge signal sent by the DMA also passes through the synchronizer, and the synchronizer can synchronize the received signal to a corresponding clock domain and then connect to the internal logic of the local clock domain, so that the metastable state of the clock domain crossing signal can be solved, and the transmission stability is improved.
The above description is of the preferred embodiment of the invention; it is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; any person skilled in the art can make many possible variations and modifications, or modify equivalent embodiments, without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention, unless the technical essence of the present invention is not departed from the content of the technical solution of the present invention.
Claims (8)
1. A data transmission method based on a DMA controller is characterized by comprising the following steps:
the CPU sends an instruction to a peripheral and the DMA controller and sets a transmission task;
responding to a data transmission request initiated by the peripheral equipment received by the DMA controller, and transporting data in a peripheral cache Buffer to a memory through a bus, or transporting the data in the memory to the peripheral cache; the data transmission request is initiated when the peripheral cache meets the data transmission condition;
responding to the DMA controller to finish data transportation based on the data transmission request, directly sending a response signal to the peripheral equipment, and waiting for the next round of data transmission request; the response signal is used for indicating the DMA controller to complete the data transmission of the current round;
responding to the DMA controller to finish n rounds of data transmission, and sending a DMA interrupt request to the CPU after finishing the transmission task set by the CPU, so that the CPU can respond to the DMA interrupt request and execute ending work conveniently; wherein n is the number of rounds required for completing data transmission between the peripheral and the memory, and n is a positive integer.
2. The method of claim 1, wherein before the DMA controller receives a peripheral initiated data transfer request, the method further comprises:
setting handshake signals between the DMA controller and the peripheral equipment, wherein different handshake signals are used for representing different data transmission directions and different data transmission types;
the CPU sends instructions to the peripheral and the DMA controller and sets a transmission task;
and when the external equipment meets the data transmission condition, generating a corresponding handshake signal and sending the data transmission request.
3. The method of claim 2, wherein in response to the DMA controller receiving a peripheral initiated data transfer request, the method further comprises:
determining a target handshake signal corresponding to the data transmission request, and matching the data transmission direction and the data transmission type of the target handshake signal;
in response to the target handshake signals being read data signals, the DMA controller reads data of the target data amount from the peripheral cache to a memory through a bus;
and in response to the target handshake signals being corresponding to write data signals, the DMA controller writes the data of the target data volume in the memory into the peripheral cache through a bus.
4. The method of claim 3, wherein the read data signals comprise at least a first read data signal rx _ single and a second read data signal rx _ burst; the rx _ single signal indicates that the data amount read in each request is single data, and the rx _ burst signal indicates that the data amount read in each request is burst data; the bit width burst and the length burst length of the burst data are specifically set by a CPU (central processing unit) in the DMA controller;
the directly sending a response signal to the peripheral in response to the DMA controller completing data transfer based on the data transfer request includes:
directly sending a first read response signal rx _ single _ ack to the peripheral after the single data is read into the memory from the peripheral cache by the DMA controller; or the like, or, alternatively,
and directly sending a second read reply signal rx _ burst _ ack to the peripheral after responding to the DMA controller reading the burst data from the peripheral cache into the internal memory.
5. The method of claim 3, wherein the write data signals comprise a first write data signal tx _ single and a second write data signal tx _ burst; the tx _ single signal indicates that the amount of data written per request is single data, and the tx _ burst signal indicates that the amount of data written per time is burst data;
the responding to the DMA controller to complete data transfer based on the data transmission request and directly sending a response signal to the peripheral equipment further comprises:
directly sending a first write acknowledgement signal tx _ single _ ack to the peripheral after the DMA controller writes the single data from the memory into the peripheral cache; or the like, or, alternatively,
and directly sending a second write acknowledgement signal tx _ burst _ ack to the peripheral after responding to the DMA controller writing the burst data from the memory into the peripheral cache.
6. The method according to claim 4 or 5, wherein the sending a DMA interrupt request to the CPU after completing a transmission task set by the CPU in response to the DMA controller completing n rounds of data transmission comprises:
responding to the DMA controller to receive the data transmission request sent by the peripheral equipment again, and continuing to carry out data carrying and send response signal operation according to the data transmission request until n rounds of data transmission are completed;
after the DMA controller finishes a transmission task set by a CPU, sending the DMA interrupt request to the CPU; after completing the transmission task set by the CPU, the peripheral sends a peripheral interrupt request to the CPU;
when the CPU receives the peripheral interrupt request, responding to the peripheral interrupt and executing the ending work of the peripheral side; when the CPU receives the DMA controller interrupt request, responding to the DMA interrupt and executing the ending work of the DMA side; and when the CPU executes the ending work of the peripheral equipment side and the DMA side, the data transmission task is finished.
7. The method of claim 1, wherein when the peripheral and the DMA controller are in different clock domains, a synchronizer is provided between the peripheral and the DMA controller, respectively, and is configured to synchronize the data transfer request and the reply signal to the respective clock domains.
8. The method of claim 5, wherein after the DMA controller sends an acknowledgement signal to the peripheral, the method further comprises:
when the peripheral receives the response signal sent by the DMA controller, determining the received target data volume; and when the received target data volume is the same as the data volume specified by the response signal and the peripheral internal cache meets the data transmission sending request again, sending the data transmission request to the DMA controller again for the next round of data transmission.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117312221A (en) * | 2023-11-28 | 2023-12-29 | 西安现代控制技术研究所 | Triggering type SPI data communication method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004145593A (en) * | 2002-10-24 | 2004-05-20 | Sony Corp | Direct memory access device, bus arbitration controller, and control method for the same |
| US20160124878A1 (en) * | 2014-11-04 | 2016-05-05 | Atmel Corporationi | Data transfer |
| CN111615692A (en) * | 2019-05-23 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Data transfer method, calculation processing device, and storage medium |
| CN113468084A (en) * | 2021-05-28 | 2021-10-01 | 北京时代民芯科技有限公司 | Multi-mode DMA data transmission system |
| CN113590512A (en) * | 2021-07-30 | 2021-11-02 | 眸芯科技（上海）有限公司 | Self-starting DMA device capable of directly connecting peripheral equipment and application |
| CN114328322A (en) * | 2022-03-17 | 2022-04-12 | 之江实验室 | DMA controller operation method capable of configuring function mode |
| CN114328316A (en) * | 2021-11-22 | 2022-04-12 | 北京智芯微电子科技有限公司 | DMA controller, SOC system and data carrying method based on DMA controller |
-
2022
- 2022-05-26 CN CN202210588217.3A patent/CN114968863A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004145593A (en) * | 2002-10-24 | 2004-05-20 | Sony Corp | Direct memory access device, bus arbitration controller, and control method for the same |
| US20160124878A1 (en) * | 2014-11-04 | 2016-05-05 | Atmel Corporationi | Data transfer |
| CN111615692A (en) * | 2019-05-23 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Data transfer method, calculation processing device, and storage medium |
| CN113468084A (en) * | 2021-05-28 | 2021-10-01 | 北京时代民芯科技有限公司 | Multi-mode DMA data transmission system |
| CN113590512A (en) * | 2021-07-30 | 2021-11-02 | 眸芯科技（上海）有限公司 | Self-starting DMA device capable of directly connecting peripheral equipment and application |
| CN114328316A (en) * | 2021-11-22 | 2022-04-12 | 北京智芯微电子科技有限公司 | DMA controller, SOC system and data carrying method based on DMA controller |
| CN114328322A (en) * | 2022-03-17 | 2022-04-12 | 之江实验室 | DMA controller operation method capable of configuring function mode |
Non-Patent Citations (2)
| Title |
|---|
| 李洪革编著: "集成电路系统设计", 北京航空航天大学出版社, pages: 218 - 222 * |
| 甲六乙: "DMA handshaking", Retrieved from the Internet <URL:https://blog.csdn.net/m0_38037810/article/details/112725524> * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117312221A (en) * | 2023-11-28 | 2023-12-29 | 西安现代控制技术研究所 | Triggering type SPI data communication method |
| CN117312221B (en) * | 2023-11-28 | 2024-03-15 | 西安现代控制技术研究所 | Triggering type SPI data communication method |
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