JP2004145593A - Direct memory access device, bus arbitration controller, and control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a direct memory access (DMA) device that controls transfer of data between devices sharing a bus independently of a CPU, a bus arbitration controller that determines a default bus master from a plurality of bus masters in dependence on bus transfer requests, and a control method therefor. <P>SOLUTION: The DMA device has data buffers 31 of, for example, 16 bytes mounted on input/output devices 14 (14-1/14-2), and data buffers 32 of, for example, 16 bytes mounted on DMA controllers 12 (12-1/12-2). A data size in a source device (the input/output device 14 in this example) and a data size in a destination device (a main memory 13 in this example) are independently controllable, so that the application of different memory access controls to the respective source device and destination device effectively uses a bus band. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a direct memory access (DMA) device that controls data transfer between devices sharing a bus without using a CPU, and a bus that determines a default bus master based on a bus transfer request from each of a plurality of bus masters. The present invention relates to an arbitration control device and a control method thereof.
[0002]
[Prior art]
In a built-in system (computer system), when transferring a large amount of data to / from an input / output device, a DMA (DMA) is used to reduce the load on a CPU (processor) and to guarantee a required data transfer speed. Direct memory access) is used. A controller that controls the DMA (hereinafter, referred to as a DMA controller) communicates with the CPU in data transfer between an input / output device and a main storage device (main memory) or between a primary memory and a secondary memory. The load on the CPU is reduced by exchanging (transferring) data independently, that is, directly without passing through the CPU.
[0003]
The DMA is used to transfer a large number of data transfers with an input / output device having a large bandwidth such as a hard disk device. In addition, in an embedded system, DMA can be used to ensure the real-time property. In recent years, as the functions of LSI have become more sophisticated, the load on the CPU in the system has increased, and in addition to supporting high-speed input / output devices such as USB (Universal Serial Bus), it has been installed in the past. Since the speed of UART (Universal Asynchronous Receiver / Transmitter) devices and the like is also increasing, a DMA controller is used for data transfer with these input / output devices.
[0004]
In most cases, a plurality of DMA controllers are mounted in an embedded system. Then, each DMA controller performs data transfer independently. In the case of an embedded system, it is necessary to minimize the time during which each DMA controller (bus master) occupies the data bus in order to ensure its real-time performance.
[0005]
Conventionally, a method has been adopted in which a DMA controller cannot independently control a method of accessing a transfer source device and a method of accessing a transfer destination device (for example, Patent Document 1). In such a DMA controller, the data size (bus width) that can be transferred by one bus access is set to the data size (bus width) of the transfer source or transfer destination device, and the transfer method also matches the characteristics of the device. Was set.
[0006]
[Patent Document 1]
Japanese Patent No. 320601
[0007]
[Problems to be solved by the invention]
However, in a conventional DMA controller that adopts a method in which the access method to the transfer source device and the access method to the transfer destination device cannot be independently controlled, the use of the bus band is limited, In some cases, it may not be possible to guarantee a sufficient data transfer speed because the data transfer characteristics of the device cannot be derived.
[0008]
Further, since the transfer bus width (data size) is limited by the transfer destination or transfer source device, the number of data transfers (bus access) in the DMA controller also increases. As a result, the time required to occupy the bus in the system increases, and the response to the data transfer request from the high-speed input / output device cannot be sufficiently ensured, or the real-time performance in the CPU or other DMA devices is affected. Will be.
[0009]
The present invention has been made in view of the above-described problems, and has as its object to provide a direct memory access device and a plurality of direct memory access devices that can guarantee a sufficient data transfer speed and reduce the occupation time of a system bus. It is an object of the present invention to provide a bus arbitration control device that determines a default bus master based on a bus transfer request from each of the bus masters, and a control method thereof.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, according to a first aspect of the present invention, a direct memory access (DMA) object is provided in a direct memory access device that controls data transfer between devices sharing a bus without using a CPU. And a data transfer method capable of independently controlling the data size of the transfer source device and the data size of the transfer destination device.
[0011]
By adopting this data transfer method, different memory access control can be applied to the transfer source device and the transfer destination device, and the bus bandwidth can be used effectively, so that one DMA controller occupies the bus. Time can be greatly reduced. As a result, the chances of other bus masters being granted a bus increase. This means that the efficiency of the entire system bus has been improved.
[0012]
According to a second aspect of the present invention, there is provided a direct memory access apparatus including a DMA controller that controls data transfer between a memory sharing a bus and a peripheral device having a specific transfer block size without using a CPU. A handshake operation for repeatedly performing data transfer with the transfer block size is performed by a DMA controller.
[0013]
In the block size DMA transfer, by performing a handshake operation corresponding to an interrupt of the CPU on the DMA controller side, the load on the CPU when performing the DMA transfer can be reduced, so that the speed of the entire system can be increased when operating the application. And the CPU can concentrate on other processing.
[0014]
According to a third aspect of the present invention, a plurality of bus masters including a CPU having a plurality of bus interfaces, and a shared bus to which the plurality of bus masters are commonly connected are provided, and a default is provided based on a bus transfer request from each of the plurality of bus masters. In a bus arbitration control device that determines a default bus master based on a bus transfer request from each of a plurality of bus masters that determine a bus master, in a period in which there is no bus transfer request from all of the plurality of bus masters, the most recent among the plurality of bus interfaces of the CPU. The bus interface that has performed the bus transfer is determined as a default bus master.
[0015]
Considering that the CPU performs as much work as possible in the determined period, during the period when there is no bus transfer request from all bus masters, that is, during the idle state, the most recent bus transfer among the bus interfaces of the CPU is performed. By determining the performed bus interface as the default bus master, the bus transfer can be started immediately, so that a handover cycle due to arbitration does not occur.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an embedded system (computer system) to which the present invention is applied.
[0017]
As is clear from FIG. 1, the embedded system according to this configuration example includes one CPU (microprocessor) 11, a plurality (for example, two) of DMA controllers 12A and 12B, an on-chip main memory 13, and a DMA controller. Two input / output (I / O) devices 14-1 and 14-2 corresponding to 12-1 and 12-2 and an external bus interface (I / F) 15 are interconnected via a system bus 16. The circuit block 10 includes a DRAM 21 and a flash (FLASH) memory 22 connected to an external bus interface 15 via an external bus 21 outside the chip of the circuit block 10.
[0018]
In the embedded system having the above configuration, the width of the system bus 16 is set to, for example, 32 bits. The input / output devices 14-1 and 14-2 are connected to the system bus 16 with an 8-bit width. The CPU 11 controls the entire system. The DMA controllers 12-1 and 12-2 perform the data transfer between the input / output devices 14-1 and 14-2 and the main memory 12, or between the DRAM 22 and the flash memory 23 without the intervention of the CPU 11. It functions to reduce the load on the CPU 11.
[0019]
Normally, the DMA controllers 12-1 and 12-2 share the system bus 16 with another bus master such as the CPU 11. The occupation right of the system bus 16 is determined by a bus arbiter (bus arbitration control device) 17. Specific functions of the bus arbiter 17 will be described later in detail. A control signal Req for a data transfer request is sent from each of the input / output devices 14-1 and 14-2 to each of the DMA controllers 12-1 and 12-2 independently. , 12-2 returns a control signal Ack for responding to control signal Req independently to each of input / output devices 14-1, 14-2.
[0020]
In response to a data transfer request from the CPU 11 or each of the input / output devices 14-1 and 14-2, the DMA controllers 12-1 and 12-2 make an inquiry (Request) to the bus arbiter 17 for a bus occupation right, and the bus arbiter 17 is authorized. (Grant), the data is transferred through the system bus 16. Data transfer by the DMA controllers 12-1 and 12-2 is performed by first receiving data from a transfer source device (data read) and sending the received data to a transfer destination device (data write). When the transfer source and transfer destination devices are in the same bus hierarchy as in the present configuration example, basically, the DMA controllers 12-1 and 12-2 perform the data read as shown in FIG. And data write are performed in order to complete the data transfer.
[0021]
In the embedded system according to this configuration example, an example is described in which two DMA controllers 12-1 and 12-2 are mounted corresponding to the two input / output devices 14-1 and 14-2. This is merely an example, and it goes without saying that three or more DMA controllers may be mounted corresponding to three or more input / output devices. In recent years, at present, about ten or more DMA controllers are mounted in accordance with the sophistication of LSIs.
[0022]
As described above, a single-chip microcomputer (LSI) incorporating an embedded system in which about ten or more DMA controllers are mounted is used by being mounted on a portable information terminal represented by, for example, a PDA (Personal Digital Assistants). . When used by being mounted on a portable information terminal, a memory stick or USB is connected as a peripheral device to a plurality of input / output devices corresponding to a plurality of DMA controllers.
[0023]
By the way, recent input / output devices often have a data buffer mounted in the device in order to improve a data transfer speed with an external communication device. In order to efficiently perform data transfer with such an input / output device, it is important that the DMA controllers 12-1 and 12-2 perform data access in consideration of the characteristics of each device. Therefore, each of the DMA controllers 12-1 and 12-2 has a data buffer of a required size. The larger the data buffer mounted on the DMA controllers 12-1 and 12-2, the higher the data transfer speed. When determining the size of the data buffer, it is necessary to consider the impact on the area.
[0024]
In the embedded system according to this configuration example, as shown in FIG. 3, a data buffer 31 of, for example, 16 bytes is provided on the input / output device 14 (14-1 / 14-2) side and the DMA controller 12 (12-1 / 12-). It is assumed that a data buffer 32 of, for example, 16 bytes is mounted in 2). Here, it is assumed that data is transferred from the input / output device 14 to the main memory 13, for example. The DMA controller 12 includes a transfer control circuit 33 and a bus I / F 34 in addition to the data buffer 32.
[0025]
In this system configuration, for example, a UART (16C550 or the like) device is used as the input / output device 14. By notifying the DMA controller 12 of an appropriate data transfer request, the input / output device 14 can handle burst transfer in units of up to 16 bytes. Here, the burst transfer means transferring a plurality of byte data collectively by continuous use of a bus cycle. Since a 16-byte data buffer 32 is similarly mounted on the DMA controller 12 side, burst transfer can be performed in units of 16 bytes at the time of data transfer.
[0026]
Here, since the bus size of the system bus 16 is 32 bits while the data size of the input / output device 14 is 8 bits, the bus width is not sufficiently utilized at the time of data writing in this data transfer. Become. Further, in the case of the conventional DMA controller, since the data size (read data size) of the transfer source device and the data size (write data size) of the transfer destination device cannot be independently controlled, FIG. As shown in (A), 32 data transfer cycles occur on the system bus, including data read and data write.
[0027]
[First Embodiment]
In view of these points, a DMA device according to the first embodiment of the present invention described below is provided.
[0028]
In the DMA device according to the present embodiment, the data size of the transfer source device (the input / output device 14 in this example) and the data size of the transfer destination device (the main memory 13 in the present example) can be independently controlled. It is characterized by adopting a simple data transfer method. By adopting this data transfer method, different memory access controls can be applied to the transfer source device and the transfer destination device to effectively use the bus band. The time occupying 16 can be greatly reduced.
[0029]
This data transfer method can be realized by dividing the bus control information of the DMA controller 12 into transfer source access and transfer destination access so that the data can be set by software. As an example, by setting the data size of the transfer source device to 8 bits and the data transfer (write data) size to the transfer destination device to 32 bits, a write transfer occurs as shown in FIG. 4B. Since the occupation time of the system bus 16 can be reduced by 8 DMA transfer cycles, bus access at the time of data writing can be greatly reduced (data integration).
[0030]
As described above, by adopting the transfer method in which the data size of the transfer source device and the data size of the transfer destination device can be independently controlled, the time for which one DMA controller occupies the system bus is reduced, and the other bus master is used. (CPUs, DMA controllers, etc.) are more likely to be authorized for the bus. This means that the efficiency of the entire system bus has been improved. The data size can be flexibly set, and the data size of the transfer source device and the data size of the transfer destination device are set under conditions that fit within the size of the data buffer 32 mounted in the DMA controller 12 (16 bytes in this example). Settings can be made.
[0031]
In data transfer, the efficiency can be improved by considering not only the data size but also the data transfer type. Various bus slave devices are connected in the embedded system. Further, a memory device such as a DRAM 22 or a flash memory 23 is connected to the outside via an external bus interface 15. Many of these memory devices employ burst transfer in order to secure a data transfer speed.
[0032]
In some cases, a DRAM or the like is mounted inside the device to improve the data transfer rate by partially expanding the data bus width. For these devices, it is possible to improve the data transfer efficiency by appropriately performing a data transfer of a transfer type suited to each characteristic, that is, a burst transfer. Also, as shown in FIG. 5, the specification is such that a burst transfer can be divided into a plurality of times and executed even for a device having a narrow bus width. The division of the burst transfer is also automatically processed in the DMA controller 12 according to the combination of the set transfer data sizes (data distribution).
[0033]
When such a transfer method based on data distribution is adopted, depending on the total number of data transfers (total data size of the transfer block) and the combination of the transfer type and data size, the transfer of data at the end of transfer (end of transfer block) is performed. The remainder (fraction) may occur. In such a case, the data transfer of the set transfer type is continued as much as possible, and finally only the remainder (fraction) has the minimum data size (8 bits in this example) and the minimum transfer type (single data transfer). Automatically to complete the transfer up to the final data.
[0034]
Specifically, as shown in FIG. 6, for example, in the case of a data size of 32 bits, 4-burst transfer, and a final data block of 15 bytes (fraction of 3 bytes), the transfer of a fractional 3 bytes is automatically performed as data. The transfer is completed by switching to the size of 8 bits. The design is such that special awareness is not required in software for such fractional processing.
[0035]
In addition, even when different byte arrays (endian) are used between the transfer source and the transfer destination, it is possible to cope by adding the information of the byte array to the transfer source and the transfer destination and performing control.
[0036]
As described above, in the DMA device according to the first embodiment, the conventional data transfer method is reviewed in order to effectively utilize the limited bus bandwidth of the embedded system and to increase the efficiency of data transfer by DMA. In the control of the source data transfer (data read) and the destination data transfer (data write), the transfer data size and the transfer type can be set independently, and different memory access control is performed for the source device and the destination device, respectively. The use efficiency of the system bus 16 can be improved in data transfer between input / output devices having different bus widths (for example, UART-main memory) in the same system.
[0037]
This immediately leads to an improvement in the data transfer efficiency of the DMA controller 12, that is, the data transfer speed. Further, since the number of bus occupation requests by the DMA controller 12 decreases, the number of bus arbitrations by the bus arbiter 17 in the system also decreases. This leads to suppression of a signal change of the system bus 16, and accordingly, it is possible to reduce power consumption.
[0038]
In a system in which many DMA controllers and other bus masters are implemented, the occupation time of the system bus requested by one bus master also affects the responsiveness of another bus master. Particularly, in the case of an embedded system, real-time performance is regarded as important, and the reduction of the occupation time of the system bus by the DMA controller or the like also has the effect of not deteriorating the real-time performance of the system (CPU).
[0039]
Also, the remainder (fraction) of data generated at the end of the transfer due to the combination of the total transfer data number and the transfer type is automatically switched to the minimum data size (8 bits in this example) and the minimum transfer type, and the data up to the final data is obtained. Completion of the transfer eliminates the need for software to pay special attention to the remainder (fraction) of the data, thereby reducing the load on the CPU 11.
[0040]
By the way, between the peripheral device (here, the input / output devices 14-1 and 14-2 are exemplified) 14 having a specific transfer block size (for example, a buffer memory size and a packet size) and the main memory 13. When performing the DMA transfer, the DMA controller 12 stops every time the transfer of data corresponding to the transfer block size of the peripheral device 14 is completed. At this time, an interrupt is generated for the CPU 11, and the CPU 11 receives the interrupt, performs an appropriate countermeasure, issues an instruction to start the DMA transfer again, and requires a handshake by software processing on the CPU 11 side.
[0041]
Specifically, as shown in FIG. 7, a transfer end interrupt is generated in the CPU 11 in response to a transfer request signal from the peripheral device 14, and upon receiving this interrupt, the CPU 11 transmits a DMA transfer to the DMA controller 12. Resume processing, that is, a transfer start instruction is sent. As described above, the CPU 11 performs the transfer resuming process of the DMA controller 12 in the interrupt routine, so that not only the transfer of all data takes time but also the other processes executed by the CPU 11 are suppressed, and as a result, the entire application is executed. Will be reduced.
[0042]
Further, after the block size transfer is repeated and the transfer of the desired data amount is completed, there is a case where the same DMA transfer is desired to be performed again from the transfer source top address of the main memory 13 which was previously set. In this case, it is necessary to reset the conditions such as the address from the CPU 11 for the DMA controller 12.
[0043]
[Second embodiment]
What has been made in view of these points is a DMA device according to a second embodiment of the present invention described below.
[0044]
FIG. 8 is a block diagram showing a configuration example of the system of the DMA device according to the present embodiment. In the drawing, the same parts as those in FIG. 1 are denoted by the same reference numerals. Here, the input / output devices 14-1 and 14-2 of FIG.
[0045]
8, the DMA controller 12 includes, for example, a counter 41 as counting means for counting a data transfer amount, a register 42 as storage means (area) for storing data of a transfer block size of the peripheral device 14, and a source address pointer 43. And a destination address pointer 44. The DMA device according to the present embodiment has a configuration in which a transfer request signal from the peripheral device 14 is directly supplied to the DMA controller 12.
[0046]
Next, data transfer (DMA transfer) in the DMA device according to the second embodiment having the above configuration will be described.
[0047]
(Handshake with peripheral devices)
First, the CPU 11 notifies the DMA controller 12 of the transfer block size of the peripheral device 14. Then, the DMA controller 12 stores the notified transfer block size in a storage device such as the register 42. The transfer block size of the peripheral device 14 may be known in advance by the DMA controller 12 as a fixed value, that is, the value may be stored in a storage device such as the register 42 in advance.
[0048]
Upon receiving a transfer start instruction from the CPU 11, the DMA controller 12 starts transferring data between the peripheral device 14 and the main memory 13 through a data path such as the system bus 16. During the data transfer period, the DMA controller 12 counts the number of transfer data with the counter 41 and compares the counted number of transfer data with the value stored in the register 42, that is, the transfer block size. Then, when the DMA controller 12 knows that the comparison results match, that is, that the transfer of data of the transfer block size of the peripheral device 14 has been completed, the DMA controller 12 automatically temporarily stops the transfer and waits for a transfer request from the peripheral device 14. .
[0049]
When the peripheral device 14 becomes ready to transfer data again, the peripheral device 14 issues a transfer request signal to the DMA controller 12. In response to this, the DMA controller 12 clears the counter 41 and restarts the data transfer. By repeating this operation, the DMA controller 12 can complete the transfer of all data without the intervention of the CPU 11.
[0050]
(Address loop)
FIG. 9 is a diagram showing an example of a change in the contents of the transfer address pointer when data is transferred from the main memory 13 to the peripheral device 14. In this example, since the data is transferred from the main memory 13 to the peripheral device 14, the transfer address of the main memory 13 is the source address pointer 43 and the transfer address of the peripheral device 14 is the destination address in the DMA controller 12 of FIG. Each is managed by the pointer 44.
[0051]
Here, the transfer size of the peripheral device 14 is 0x100. The transfer address pointer of the main memory 13, that is, the source address pointer 43 starts from 0x1000 and advances to 0x10ff, and the transfer address pointer of the peripheral device 14, that is, the destination address pointer 44 advances from 0x8000 to 0x80ff, and the data in this memory area is The data is sequentially read from the main memory 13 by the DMA controller 12 and written to the peripheral device 14.
[0052]
When the transfer of data of the transfer block size (0x100) is completed, the source address pointer 43 on the main memory 13 side is 0x1100, but the peripheral device 14 uses the destination address on the peripheral device 14 side again from 0x8000. Return the pointer 44 to 0x8000. When the transfer amount reaches the transfer block size of the peripheral device 14, the DMA controller 12 suspends the data transfer, and sends a transfer request signal for notifying the DMA controller 12 that the peripheral device 14 is ready to transfer again. , And waits until the DMA controller 12 receives it from the peripheral device 14.
[0053]
Upon receiving the transfer request signal, the DMA controller 12 restarts the data transfer from the source address pointer 43 on the main memory 13 side from 0x1100 and the destination address pointer 44 on the peripheral device 14 side from 0x8000. That is, the source address pointer 43 is continuously increased on the main memory 13 side, while the destination address pointer 44 is looped on the peripheral device 14 side. Thereafter, the above-described series of processing is repeated until transfer of all data requested by the application is completed.
[0054]
In this manner, the DMA controller 12 loops the transfer address pointer on the peripheral device 14 side, that is, the destination address pointer 44, with the transfer size (0x8000 to 0x80ff in this example), and every time the transfer of the block size is completed. By automatically waiting for the transfer to be resumed, the transfer of all data can be completed without the intervention of the CPU 11.
[0055]
FIG. 10 is a diagram showing an example of a change in the contents of the transfer address pointer when data is transferred from the peripheral device 14 to the main memory 13. In this case, basically, the operation is the same as the operation when data is transferred from the main memory 13 to the peripheral device 14 (see FIG. 9).
[0056]
Note that, depending on the specifications of the peripheral device 14, the address read / written by the DMA controller 12 is fixed, and the same data transfer as in the above example is performed by reading / writing data of the transfer block size for one address. Sometimes you can. In this case, the transfer address pointer on the peripheral device 14 side may be fixed instead of a loop.
[0057]
(Reload function)
After a series of block size transfer described above is repeated and transfer of a desired amount of data is completed, there is a case where a similar DMA transfer is desired to be performed again from the transfer source start address of the main memory 13 previously set. Therefore, the DMA device according to the present embodiment employs a configuration in which the DMA controller 12 has a reload function of reproducing a series of settings from the CPU 11 at the time of DMA transfer.
[0058]
By providing the DMA controller 12 with the reload function in this way, the CPU 11 can restore the previously set values only by giving a simple reset instruction to the DMA controller 12. The load can be reduced. This reload function can be realized by a method in which a register mapped to a specific address is provided in the DMA controller 12 and a specific bit of the register is operated from the CPU 11. Since reloading is performed by an explicit instruction from the CPU 11, whether or not to reload can be dynamically determined by a user program of the CPU 11.
[0059]
As described above, in the DMA device according to the second embodiment, when the peripheral device 14 has a specific transfer block size (for example, a buffer memory size or a packet size) and repeatedly performs data transfer with the transfer block size. The conventional CPU 11 performs a handshake operation by the CPU 11 on the side of the DMA controller 12 having a storage area (register 42) for storing the transfer block size of the peripheral device 14 and a counter 41 for counting the transfer amount. The software processing that has been performed can be automatically processed by hardware by the DMA controller 12. As a result, the load on the CPU 11 when performing the DMA transfer can be reduced, so that the speed of the entire system can be increased when the application is operated.
[0060]
FIG. 11 shows the time required to transfer a fixed amount of data (DMA transfer time) between a DMA device having a conventional DMA controller and a DMA device having a DMA controller having a block DMA transfer function according to the present embodiment. It is a schematic diagram which shows the comparison result of (speed).
[0061]
In the conventional DMA transfer, an interrupt occurs in the CPU 11 in response to a transfer request signal from the peripheral device 14, and this interrupt causes the CPU 11 to perform the transfer restart processing of the DMA controller 12 in an interrupt routine. In addition to this, the other processes executed by the CPU 11 are pressed down, and as a result, the speed of the entire application is reduced. On the other hand, in the block size DMA transfer, a process corresponding to an interrupt of the CPU 11 is processed by hardware on the side of the DMA controller 12, so that there is no overhead per block size and the CPU 11 can concentrate on other processes. .
[0062]
Further, when the CPU 11 needs to repeatedly perform the same setting for the module (in this example, the DMA controller 12) for which the CPU 11 performs a series of settings during the operation of the application, for example, the setting value is changed during the operation. In the case of a change, the module is provided with a function of reproducing the setting in the same manner as the first time, that is, a reload function, so that the procedure of resetting by the CPU 11 is omitted, and a simple instruction is given from the CPU 11 to the module. Thus, the load on the CPU 11 can be reduced. For example, even if it is necessary to reset the address or the like to the DMA controller 12 after the completion of the data transfer, the DMA controller 12 has a reload function, and the setting can be restored by a simple operation, or the setting can not be restored. It is also possible to transfer data continuously from the address value at that time.
[0063]
Up to this point, two embodiments of the DMA device have been described. Hereinafter, a bus arbiter (bus arbitration control device) 17 that arbitrates a plurality of bus masters (the CPU 11, the DMA controllers 12-1, 12-2, and the like) with respect to the system bus 16, which is a shared bus, will be described.
[0064]
As an arbitration method, there is a method in which priorities are assigned to the respective bus masters, and a bus use right (bus occupation right) is given to the bus master having the highest priority among the bus masters requesting the bus transfer. When there is no bus use request from any bus master (idle state), the bus use right is given to one determined default bus master.
[0065]
When selecting the default bus master, it is advantageous to select the bus master that will make the bus transfer request most as the default bus master. The reason is that when the bus master issues a bus transfer request while the shared bus is in the idle state, if the bus master is the default bus master, the overhead in the bus arbiter 17 is reduced, resulting in an increase in bus efficiency.
[0066]
To determine the default bus master,
{Circle around (1)} A method in which the bus master that has performed the bus transfer immediately before the shared bus enters the idle state becomes the default bus master (for example, see Japanese Patent Application Laid-Open No. 5-250311)
{Circle over (2)} A method of setting the bus master that has performed the most bus transfer among the past several bus transfers on the shared bus as the default bus master (for example, refer to JP-A-2000-35443)
and so on.
[0067]
However, according to the determination method (1), if the bus master that has performed the bus transfer immediately before the idle state is the bus master with the lowest bus transfer request frequency, there is a possibility that another bus master with the next highest bus transfer request makes the transfer request. high. In the determination method (2), several past transfer histories are stored for all the bus masters such as the CPU 11 and the DMA controllers 12-1 and 12-2, and the determination is made based on the transfer histories. Therefore, in an embedded system including many bus masters, logic complexity is expected.
[0068]
[Third embodiment]
In view of these points, a bus arbitration architecture according to a third embodiment of the present invention described below has been made.
[0069]
FIG. 12 is a block diagram showing a configuration example of a system of a DMA device to which the bus arbitration architecture according to the present embodiment is applied. In the drawing, the same parts as those in FIG. 1 are denoted by the same reference numerals. Here, a CPU (microprocessor) 11 and two DMA controllers 12-1 and 12-2 are exemplified as a plurality of bus masters, and the DMA controllers 12-1 and 12-2 are bus masters 12-1 and 12-2. As shown.
[0070]
As shown in FIG. 12, the CPU 11 has a plurality of bus interfaces serving as bus masters, for example, two bus interfaces 111 and 112. Therefore, in the embedded system according to this configuration example, a total of four bus masters including two bus interfaces 111 and 112 and other bus masters, for example, two DMA controllers 12-1 and 12-2, share one system bus 16. Will share.
[0071]
The bus arbiter 17 performs control (bus arbitration) so that there is always one bus master performing bus transfer so that data collision does not occur in the system bus (shared bus) 16. That is, arbitration handover in which each bus master issues a bus transfer request REQ to the bus arbiter 17 and the bus arbiter 17 gives a bus transfer permission GRNT to each bus master in response to the request REQ is performed. -1, 12-2 and the bus arbiter 17.
[0072]
FIG. 13 is a block diagram illustrating a specific configuration example of the bus arbiter 17. As is clear from FIG. 13, the bus arbiter 17 according to the present configuration example determines the priority order according to the bus transfer requests REQ # 1 to # 4 input from each of the bus masters and outputs the bus transfer permission GRNT # 1 to GRNT # 4. And a pre-grant control circuit 172 that determines a default bus master based on the bus transfer permission GRNT # 1 and GRNT # 2.
[0073]
In the bus arbiter 17 configured as described above, the bus transfer requests REQ # 1 to REQ # 4 are input to the round robin control circuit 171 from each of the bus masters, and the bus transfer requests REQ # 1 to # 4 change the priority in the round robin control circuit 171. When determined, the bus transfer permission GRNT # 1 to # 4 that is adapted according to the priority becomes active. At this time, of the bus transfer permission GRNTs # 1 to # 4, only the values of the bus transfer permission GRANT # 1 and # 2 of the bus interfaces 111 and 112 of the CPU 11 are input to the pregrant control circuit 172.
[0074]
Here, inputting only the value of the bus transfer permission GRANT # 1, # 2 among the bus transfer permission GRNT # 1 to # 4 to the pregrant control circuit 172 means that the bus interface 111, 112 of the CPU 11 is connected to another bus interface 111, 112. This means that the bus master is determined as the default bus master in preference to the bus master. This is in consideration of the fact that the CPU 11 performs as much work as possible during a predetermined period. When the bus transfer grants GRANT # 1 and # 2 are input to the pre-grant control circuit 172, the pre-grant control circuit 172 determines the bus interface 111 and the bus interface 112 based on the values of the bus transfer allowances GRANT # 1 and # 2. Which is the default bus master is determined.
[0075]
FIG. 14 is a block diagram illustrating a specific configuration example of the pregrant control circuit 172. As apparent from FIG. 14, the pregrant control circuit 172 according to the present configuration example determines which of the bus interfaces 111 and 112 performs the bus transfer from the value of the bus transfer permission GRANT # 1 and GRANT # 2. The circuit 1711 has a configuration including a circuit 1711 and a storage circuit 1722 that stores the determination result of the bus transfer determination circuit 1711 until one of the bus transfers occurs next.
[0076]
In the pregrant control circuit 172 having the above configuration, the bus transfer determination circuit 1711 determines the bus interface 111 and the bus interface from the values of the bus transfer permission GRNT # 1 and # 2 corresponding to the priority determined by the round robin control circuit 171. It is determined which of 112 is to perform the bus transfer. This determination result is stored in the storage circuit 1722 until the next bus transfer of one of the bus interfaces 111 and 112 occurs. As a result, the bus master corresponding to the determination result stored and held in the storage circuit 1722 becomes the bus master that has performed the bus transfer most recently.
[0077]
Here, the bus interface that has performed the most recent bus transfer among the bus interfaces 111 and 112 of the CPU 11 is determined as the default bus master. The bus transfer that has been performed most recently will make another bus transfer request. It is based on that prediction. Then, the determination result stored and held in the storage circuit 1722 is supplied to the round robin control circuit 171 as default bus master information DEF. Then, the round robin control circuit 171 determines the bus master specified by the default bus master information DEF of the bus interfaces 111 and 112, that is, the bus master that has performed the most recent bus transfer, as the default bus master.
[0078]
In an idle period when there is no bus master requesting the next bus transfer, that is, in a period when there is no bus transfer request from all bus masters, the bus corresponding to the determination result (default bus master information DEF) stored in the storage circuit 1722. The transfer permission GRNT becomes active. Thereafter, when the bus master that first requests the bus transfer is the default bus master, the bus transfer can be started immediately because the bus transfer permission GRNT is active, and a handover cycle due to arbitration does not occur.
[0079]
As described above, in the bus arbiter 17 according to the third embodiment, in consideration of the fact that the CPU 11 performs as much work as possible during a predetermined period, the bus arbiter 17 of the CPU 11 does not perform a bus transfer request from all bus masters. By determining the bus interface that has performed the bus transfer most recently among the interfaces 111 and 112 as the default bus master, the bus transfer can be started immediately. Therefore, a handover cycle due to arbitration does not occur, and the bus transfer request of the CPU 11 is not generated. Bus handover cycle at the time can be reduced.
[0080]
Further, by predicting the next bus master by the default bus master determination architecture when the CPU 11 has a plurality of bus interfaces (two in this example) serving as bus masters, the bus transfer can be started immediately, so that the handover by arbitration is performed. An overcycle does not occur, and the bus handover cycle during the bus transfer of the CPU 11 can be reduced.
[0081]
【The invention's effect】
As described above, according to the present invention, by adopting a data transfer method capable of independently controlling the data size of the transfer source device and the data size of the transfer destination device to be subjected to DMA, Since different buses can be used effectively by applying different memory access controls to the transfer destination device, a sufficient data transfer speed can be guaranteed and the occupation time of the system bus can be reduced.
[0082]
In addition, by performing a handshake operation corresponding to an interrupt of the CPU in the block size DMA transfer on the DMA controller side, the load on the CPU in performing the DMA transfer can be reduced. Can be achieved. Further, during a period in which there is no bus transfer request from all the bus masters, the bus interface that has performed the most recent bus transfer among the CPU bus interfaces can be determined as the default bus master, so that the bus transfer can be started immediately. The bus handover cycle at the time of a bus transfer request of the CPU can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an embedded system (computer system) to which the present invention is applied.
FIG. 2 is a diagram showing a cycle of a basic transfer of a DMA controller.
FIG. 3 is a block diagram illustrating a configuration example of a main part in the DMA device according to the first embodiment of the present invention.
4A and 4B are diagrams showing a data read cycle and a data write cycle. FIG. 4A shows a case where the transfer source data size and the transfer destination data size cannot be controlled independently, and FIG. Each case of the transfer method is shown.
FIG. 5 is a conceptual diagram of a transfer method based on data distribution.
FIG. 6 is a conceptual diagram of automatic processing of a data fraction.
FIG. 7 is a block diagram illustrating a configuration example of a general DMA transfer system.
FIG. 8 is a block diagram illustrating a configuration example of a system of a DMA device according to a second embodiment of the present invention.
FIG. 9 is a diagram showing an example of a change in the contents of a transfer address pointer when data is transferred from a main memory to a peripheral device.
FIG. 10 is a diagram showing an example of a change in the contents of a transfer address pointer when data is transferred from a peripheral device to a main memory.
FIG. 11 is a schematic diagram showing a comparison result of a time required to transfer a certain amount of data by a conventional DMA transfer and a block DMA transfer.
FIG. 12 is a block diagram illustrating a configuration example of a system of a DMA device to which a bus arbitration architecture according to a third embodiment of the present invention is applied.
FIG. 13 is a block diagram illustrating a specific configuration example of a bus arbiter.
FIG. 14 is a block diagram illustrating a specific configuration example of a pre-grant control circuit.
[Explanation of symbols]
11 CPU, 12, 12-1, 12-2 DMA controller, 13 main memory, 14, 14-1, 14-2 input / output device (peripheral device), 16 system bus (shared bus), 17 … Bus arbiter (bus arbitration control device)

Claims (14)

A direct memory access device for controlling data transfer between devices sharing a bus without using a CPU,
A direct memory access device comprising a DMA controller capable of independently controlling a data size of a transfer source device and a data size of a transfer destination device to be subjected to direct memory access (DMA). 2. The direct memory access device according to claim 1, wherein the DMA controller sets a data transfer type according to respective characteristics of the transfer source device and the transfer destination device. 3. The direct memory access device according to claim 2, wherein the transfer type is a burst transfer. 4. The direct memory access device according to claim 3, wherein the DMA controller executes burst transfer for a device having a narrow bus width in a plurality of times. When there is a data remainder at the end of the transfer with respect to the total data transfer number due to the set transfer type, the DMA controller automatically determines the remaining transfer number and switches to the transfer with the minimum data size. 3. The direct memory access device according to claim 2, wherein: 6. The direct memory access device according to claim 5, wherein the set transfer type is a burst transfer that is executed by being divided into a plurality of times. A direct memory access device including a DMA controller for controlling data transfer between a memory sharing a bus and a peripheral device having a specific transfer block size without using a CPU,
The DMA controller has storage means for storing data of the transfer block size, and counting means for counting the amount of data transferred between the transfer source device and the transfer destination device, A direct memory access device that performs a handshake operation when repeatedly performing data transfer. 8. The method according to claim 7, wherein the DMA controller has a function of reproducing a series of settings from the CPU at the time of DMA transfer, and reproduces the series of settings only by receiving a reset instruction from the CPU. A direct memory access device as described. A plurality of bus masters including a CPU having a plurality of bus interfaces;
A shared bus to which the plurality of bus masters are connected in common,
A bus arbitration control device that determines a default bus master based on a bus transfer request from each of the plurality of bus masters,
A bus arbitration control device, wherein a bus interface that has recently performed a bus transfer among the plurality of bus interfaces of the CPU is determined as a default bus master during a period in which there is no bus transfer request from all of the plurality of bus masters. . A control circuit that determines a priority order according to a bus transfer request from each of the plurality of bus masters and outputs a bus transfer permission to each of the plurality of bus masters;
A bus transfer determination circuit that determines which of the bus interfaces performs a bus transfer from a value of the bus transfer permission for the plurality of bus interfaces;
A storage circuit for storing and holding the determination result of the bus transfer determination circuit until the next bus transfer occurs,
10. The bus arbitration control according to claim 9, wherein the bus transfer permission corresponding to the determination result stored in the storage circuit is activated during a period in which there is no bus transfer request from all of the plurality of bus masters. apparatus. A method of controlling a direct memory access device that controls data transfer between devices sharing a bus without using a CPU,
A method for controlling a direct memory access device, wherein the data size of a transfer source device and the data size of a transfer destination device to be subjected to direct memory access (DMA) are independently controlled. The method of controlling a direct memory access device according to claim 11, wherein a data transfer type is set according to each characteristic of the transfer source device and the transfer destination device. A method for controlling a direct memory access device including a DMA controller that controls data transfer between a memory sharing a bus and a peripheral device having a specific transfer block size without using a CPU,
A method of controlling a direct memory access device, wherein a handshake operation when repeatedly performing data transfer with the transfer block size is performed by the DMA controller. A plurality of bus masters including a CPU having a plurality of bus interfaces;
A shared bus to which the plurality of bus masters are connected in common,
A control method of a bus arbitration control device that determines a default bus master based on a bus transfer request from each of the plurality of bus masters,
A bus arbitration control device, wherein a bus interface that has recently performed a bus transfer among the plurality of bus interfaces of the CPU is determined as a default bus master during a period in which there is no bus transfer request from all of the plurality of bus masters. Control method.

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