KR100531324B1 - Apparatus for memory interface and method for the same - Google Patents

Abstract

The present invention relates to a memory interface device and method for controlling access of a memory in a digital TV receiver. In particular, the present invention writes data continuously to the corresponding item of the write data queue if the memory write command and the memory write address in the memory write command are contiguous to the memory write address in the previous memory write command. In the case of the memory read command, if the address corresponding to the memory read address in the memory read command is in the write data queue, the data of the corresponding item of the write data queue is read and transferred to the system bus. Is in the read data buffer. If present, data is read from the read data buffer and transferred to the system bus. If not, data is read from memory and stored in the read data buffer and transferred to the system bus.

Description

Apparatus for memory interface and method for the same

The present invention relates to a memory interface device and method for controlling access of a memory in a digital TV receiver.

Recently, data processing systems of digital TV receivers are being developed in the form of SOC (System On Chip). In other words, it integrates existing data processing system functions with external CPU and peripheral functions into one chip.

Therefore, in the past, a data buffer memory was used for a data processing system chip and an operation memory was used for an external CPU. However, in the recent SOC type data processing system chip, a memory for operation and a data buffer memory are used as one memory. It has a shared memory structure.

As described above, in the digital TV receiver having the shared memory, the memory usage of each block, that is, memory access units (MAUs), is large.

In this case, when the MAUs are directly connected to the system bus and a general memory controller is used, a bottleneck is generated in the memory side.

In order to solve this problem, as shown in FIG. 1, the memory controller is not connected directly to the system bus but as an independent block, and memory access is performed using a special command such as an arbitration request in each MAU. This command is mostly optimized for burst memory access mode due to the characteristics of digital TV.

FIG. 1 illustrates an example in which low-memory MAUs are directly connected to a system bus, and memory-intensive MAUs are directly connected to a system bus through a memory controller, rather than directly to the system bus.

MAUs connected directly to the system bus may include, for example, a CPU embedded in a chip, a direct memory access controller (DMAC), a general purpose input output (GPIO), a universal asynchronous receiver transmitter (UART), a vectored interrupt controller (VIC), and the like. to be. In addition to the MAUs described above, other MAUs may be connected directly to the system bus and this is not important and is only shown briefly in the figures.

In addition, MAUs connected to a memory control unit not directly connected to the system bus are, for example, a system decoder, a video decoder, an audio decoder, a graphics control unit, a format converter, and the like.

In this case, the MAUs connected to the memory controller must use a system bus to access shared memory. In order to use the system bus, a system bus right of use must be requested to the memory controller.

The memory controller grants the use of the system bus to only one of the MAUs participating in the system bus arbitration to access the shared memory.

That is, any MAU of the plurality of MAUs first requests a memory controller to access the shared memory when attempting to write data to or read data from the shared memory. At this time, if there is one MAU requesting to access the shared memory, the memory controller grants the MAU the right to use the system bus to access the memory. However, if at least two MAUs simultaneously request memory accesses, the access order must be determined. That is, the memory controller checks the request from each MAU and then determines which MAU request to process first. The determined MAU is then licensed to the system bus to access shared memory.

In this case, the memory controller may process a request from each MAU by giving priority to it, or may process the request first, or a mixture of the two methods.

In addition, in FIG. 1, the role of the memory interface unit is responsible for the memory access of the CPU by providing an appropriate interface between the system bus and the memory control unit.

At this time, in the case of a CPU, a burst memory access, that is, an operation of continuously reading or writing a sequential address, is most of the time. In this case, if the design of the memory interface shown above is not optimized, it will adversely affect the performance of the CPU, and thus cause the performance of the system as a whole.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to optimize the design of the memory interface unit so that the MAU writes or reads data to the memory in a minimum time when a memory access command is issued, and its In providing a method.

According to an aspect of the present invention, there is provided a memory interface device including: a write data queue configured to include a plurality of items and temporarily store data input together with a memory write command before writing to the memory; A read data buffer for temporarily storing data read from the memory or write data queue and then transmitting the read data buffer to a system bus; When a memory write command is input from a specific MAU through a system bus, data write of the write data queue and memory write of data stored in the write data queue are controlled. When a memory read command is input, data is stored in the memory or write data queue. It is characterized in that it comprises a control unit for determining whether to read and store the data stored in the read data buffer to be transmitted to the system bus or transfer the data stored in the read data buffer directly to the system bus.

When the memory write command is input, the controller checks whether the write data queue is a pool and waits until it is a pool, and if not, writes the data requested by the memory write command to an empty item of a write data queue, and writes a memory. Ending the command is characterized in that.

When the memory write command is input, the controller transfers the data requested by the memory write command if the write data queue is not full and the memory write address of the data requested by the memory write command is contiguous with the memory write address of the previous memory write command. The data requested by the memory write command is continuously written to the same item of the stored write data queue.

When the memory write command is input, the controller determines that the data requested by the previous memory write command is not the write data queue and the memory write address of the data requested by the memory write command is not continuous to the memory write address of the previous memory write command. Validate an item of the stored write data queue, and write the data requested by the memory write command to the next item of the write data queue.

The controller may write data of a valid item among the items of the write data queue to a memory, and invalidate a corresponding item of the write data queue when memory writing is completed.

When the memory read command is input, if the memory read address included in the memory read command is in the write data queue, the controller reads data from the corresponding item of the write data queue, transmits the data to the system bus, and terminates the memory read command. It is characterized by.

When the memory read command is input, the controller stores data for the memory read address included in the memory read command in the read data buffer, and if the read data buffer is valid, the controller stores the corresponding data in the read data buffer. Transfer to the bus and end the memory read command.

If a memory read command is input, the controller reads data from the memory, stores the data in the read data buffer, and transmits the data to the system bus if the memory read address included in the memory read command is not in the write data queue and the read data buffer. And end the memory read command.

The controller may validate the read data buffer when the data read from the memory is stored in the read data buffer.

Memory write interface method according to the present invention,

Checking whether the write data queue is a pool if the input command is a memory write command and waiting until the pool is not the pool;

Determining that the memory write address of the data requested by the memory write command is contiguous with the memory write address of the previous memory write command if it is determined that the pool is not full;

Continuously writing data requested by the memory write command to the same item of the write data queue in which the data requested by the previous memory write command is stored;

Validating an item of a write data queue in which data requested by a previous memory write command is stored, and writing the data requested by the memory write command to a next item of the write data queue if it is determined that the data is not continuous; And

And writing data of a valid item among the items of the write data queue into a memory, and invalidating a corresponding item of the write data queue when memory writing is completed.

Memory read interface method according to the present invention,

Determining whether a memory read address included in the memory read command is in a write data queue when the input command is a memory read command;

If it is determined that the specific item is in the write data queue and the item is in a valid state, reading data from the corresponding item in the write data queue, transferring the data to a system bus, and terminating a memory read command;

Determining whether data for a memory read address included in the memory read command is stored in a read data buffer when it is determined that the write data queue is not in the write data queue;

If the read data buffer is stored in the read data buffer and the read data buffer is in a valid state, transferring corresponding data of the read data buffer to a system bus and terminating a memory read command; And

If the memory read address included in the memory read command is not in the write data queue and the read data buffer, reading data from the memory, storing the data in the read data buffer, transmitting the data to the system bus, and terminating the memory read command. Characterized in that made.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

2 is a block diagram illustrating a memory interface device according to the present invention, which includes a system bus interface 210, a memory controller interface 220, a comparator 230, a write data queue 240, and The read data buffer 250 is configured. Here, the system bus interface unit 210, the memory control unit interface unit 220, and the comparison unit 230 are referred to as a control unit for controlling the write data queue 240 and the read data buffer 250.

The system bus interface unit 210 is in charge of the interface with the system bus, and interprets commands coming from the system bus and operates accordingly. For example, when a memory write command is received, data is written to the write command queue 240 in cooperation with the comparator 230, and when a memory read command is received, the data read buffer 250 is interlocked with the comparator 230. Read the data and pass it to the system bus.

The memory controller interface 220 is responsible for the interface with the memory controller. That is, the interface with the memory control unit is made by using a special command, which is composed of an address, the number of data to be read, a byte mask, and the like. The minimum unit of data read at one time is fixed to 16 bytes and the maximum number of reads is 32 X 16 bytes. The reason for this is that MAUs that access memory in the case of SOC for digital TVs access the memory in a burst and memory access frequency is very high.

The write data queue 240 is a block for temporarily storing data input together with a memory write command on a system bus before writing to the shared memory. The write data queue is assumed to be composed of eight items in one embodiment. At this time, each item is an area for storing data to be written to memory, an area for storing a corresponding memory write address, an area for storing data size to be written to memory, and a valid bit area for indicating whether or not the current queue item is valid. It is composed. That is, the valid bit can be known whether or not the corresponding cue item is valid.

The read data buffer 250 temporarily stores data read from the shared memory in interaction with the memory controller interface 220. The size of the read data buffer is assumed to be 64 bytes in one embodiment. The reason for this is that as the size of the buffer increases, the hit ratio increases, but the gate size increases rapidly. Therefore, in order to solve both problems effectively, an appropriate size, 64 bytes, was determined through experiments. In addition, there is a valid bit in the read data buffer 250 to determine whether the data read from the current memory is valid. Similarly, the valid bit can be used to determine whether the read data buffer is valid.

The comparator 230 interacts with the system bus interface 210 and interprets a command input through the system bus to check whether data related to the corresponding read address is in the write data queue when the memory read command is performed. Based on the test result, the controller decides whether to refresh the data from memory to the system bus or to reduce the data read to the system bus. It also includes logic to invalidate and read new read data after some time.

The present invention configured as described above will be described in detail with reference to the flowchart of FIG. 3 showing the memory writing process according to the memory write command and the flowchart of FIG. 4 showing the memory reading process according to the memory read command.

First, the process of writing data to shared memory is explained.

MAU trying to access memory For example, the CPU issues a memory write command when trying to write data to memory. The memory write command is input to the system bus interface unit 210 through the system bus. When a memory write command is received from the system bus (step 301), the system bus interface unit 210 outputs the memory write command to the comparator 230. When the memory write command is input, the comparison unit 230 checks whether the write data queue 240 is full or not (step 302). The write data queue 240 is a pool when data is stored in all eight items. Thus, if the write data queue 240 is full, wait until the write data queue 240 is not full. If it is determined in step 302 that the write data queue 240 is not full, the data to be written to the memory is written to an empty item of the write data queue, and the write command is completed.

In this case, in order to efficiently write data to the memory, the comparator 230 has another memory write command before the memory write command, and if the write data queue is not full, the memory write address included in the memory write command is transferred. It is determined whether the write address of the memory write command is continuous (step 303).

If it is determined in step 303 that the current memory write address is contiguous with the write address of the previous memory write command, the corresponding item of the write data queue 240 storing the data input together with the previous memory write command, that is, the data in the current item. Write (step 304).

If it is determined in step 303 that the write address is not contiguous, then the valid bit of the current queue item of the write data queue 240 is made valid and data is written to the next item (step 305).

In this case, the memory controller interface 220 continuously checks each item of the write data queue 240. If there is an item having a valid bit valid (step 306), data of a valid item is written to the memory through the memory controller based on the information of the valid item. When the data write to the memory is completed, the valid bit of the corresponding item of the write data queue 240 is invalidated (step 307). This is to allow new data to be written.

This effectively writes memory write commands to the pipeline so that data can be written to memory without any delay in terms of the system bus.

Meanwhile, when a memory read command is input through the system bus, the system bus interface unit 210 outputs the read command to the comparator 230 (step 402). When the memory read command is input, the comparator 230 checks whether the memory read address included in the memory read command is in the write data queue 240 (step 402). At this time, the items of the write data queue 240 to be checked must have a valid bit valid.

If the memory read address is in the write data queue 240 in step 402, the data of the queue item is read and put on the system bus to complete the memory read command (step 403).

If the memory read address is not in the write data queue 240 in step 402, the data for the memory read address is stored in the read data buffer 250, and at this time, the read data buffer 250 is checked to be valid ( Step 404).

In step 404, if the data for the memory read address is stored in the read data buffer 250 and the read data buffer 250 is valid, the data of the corresponding address among the data in the read data bus 250 is read. Read and put on system bus and end memory read command (step 405).

On the other hand, if either of the two conditions are not satisfied in step 404, that is, if the data for the memory read address is not in the read data buffer 250, or if the read data buffer 250 is invalid, the memory controller interface unit ( 220) to read data from the corresponding read address in memory. At this time, the read data is stored in the read data buffer 250 and loaded on the system bus (step 406). Then, the valid bit of the read data buffer 250 is converted into a valid state and the memory read command is terminated (step 407).

This allows memory read commands to be processed quickly, which can improve the performance of digital TV receivers.

As described above, the present invention optimizes the design of the memory interface unit so that the CPU writes or reads data at a minimum time when the CPU issues a memory access command, thereby not degrading the performance of the CPU.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

In addition, since the present invention has been described through the preferred embodiment of the present invention, in view of the technical difficulty aspects of the present invention, those having ordinary skill in the art can easily and other embodiments of the present invention. Other variations can be made. Therefore, it is apparent that all of the embodiments and variations cited in the above description belong to the claims of the present invention.

As described above, according to the memory interface device and the method according to the present invention, in the case of the memory write command, it is determined whether the memory write address in the memory write command is contiguous with the memory write address in the previous memory write command, Write data sequentially to the corresponding item in the queue, otherwise validate the current item and write data to the next item. In addition, if there is a valid item in the write data queue, data of a valid item is written to the memory and the item is invalidated. By doing this, the memory write command is pipelined so that data can be written to the memory without any delay in terms of the system bus.

In the case of the memory read command, if there is an address in the write data queue that matches the memory read address in the memory read command, the data of the corresponding item is read and transferred to the system bus. Check that it is in the read data buffer. If present, data is read from the read data buffer and transferred to the system bus. If not, data is read from memory and stored in the read data buffer and transferred to the system bus. By doing so, the memory read command can be processed in a short time, thereby improving the performance of the digital TV receiver.

As such, the present invention can improve the overall system performance by increasing the memory access performance of the CPU in the SOC for digital TV. In addition, the present invention is applicable to all SOCs as well as SOCs for digital TVs, and is effective because it can lead to high performance by adding a small number of gate sizes.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

1 is a schematic diagram of a typical digital TV receiver

2 is a block diagram illustrating a memory interface device in accordance with the present invention.

3 is a flowchart illustrating a data writing process according to a memory write command of the present invention.

4 is a flowchart illustrating a data reading process according to a memory read command of the present invention.

Explanation of symbols for main parts of the drawings

210: system bus interface unit

220: memory controller interface unit

230: comparison unit

240: write data queue

250: read data buffer

Claims (16)

A memory interface device of a data processing system comprising a memory and a plurality of memory access units (MAUs) for writing data to or reading data from the memory via a system bus, A write data queue comprising a plurality of items and temporarily storing data input together with a memory write command before writing to the memory; A read data buffer for temporarily storing data read from the memory or write data queue and then transmitting the read data buffer to a system bus; And When a memory write command is input from a specific MAU through a system bus, the data write of the write data queue and the memory write of the data stored in the write data queue are controlled. When the memory read command is input, data is written from the memory or the write data queue. And a controller for determining whether to read the data stored in the read data buffer and transfer the data stored in the read data buffer or directly to the system bus. The method of claim 1, wherein each item of the write data queue is And an area in which data to be written to the memory is stored, an area in which a corresponding memory write address is stored, an area in which a data size to be written in the memory is stored, and a valid bit area indicating whether a current queue item is valid or not. Memory interface device. The method of claim 1, The read data buffer includes a valid bit area indicating whether or not data read from the memory is valid. The method of claim 1, wherein the control unit When a memory write command is input, it checks whether the write data queue is a pool and waits until it is not a pool, otherwise writes the data requested by the memory write command to an empty item of a write data queue, and terminates the memory write command. And a memory interface device. The method of claim 1, wherein the control unit When a memory write command is input, if the write data queue is not full and the memory write address of the data requested by the memory write command is contiguous with the memory write address of the previous memory write command, the data requested by the memory write command is transferred to the previous memory write command. Memory interface device, characterized in that the data requested in the continuous write to the same item of the write data queue stored. The method of claim 1, wherein the control unit When a memory write command is input, write data in which the data requested by the previous memory write command is stored unless the write data queue is not full and the memory write address of the data requested by the memory write command is not contiguous with the memory write address of the previous memory write command. Validating an item of a queue, and writing data requested in the memory write command to a next item of the write data queue. The method of claim 1, wherein the control unit And writing data of a valid item among the items of the write data queue into a memory, and invalidating a corresponding item of the write data queue when memory writing is completed. The method of claim 1, wherein the control unit When a memory read command is input, when a memory read address included in the memory read command is in a write data queue, data is read from a corresponding item of the write data queue, transmitted to the system bus, and the memory read command is terminated. Memory interface device. The method of claim 8, And a corresponding item of a write data queue for reading the data should be in an enabled state. The method of claim 1, wherein the control unit When a memory read command is input, if the data for the memory read address included in the memory read command is stored in a read data buffer and the read data buffer is valid, the corresponding data of the read data buffer is transferred to the system bus. And end the memory read command. The method of claim 1, wherein the control unit When the memory read command is input, if the memory read address included in the memory read command is not in the write data queue and the read data buffer, data is read from the memory, stored in the read data buffer, transferred to the system bus, and memory read. And end the command. The method of claim 11, wherein the control unit And when the data read from the memory is stored in a read data buffer, validating the read data buffer. In the memory interface method of controlling the internal write data queue and read data buffer to write or read data to and from the memory when a memory write command or a memory read command is input from a specific memory access unit (MAU) through the system bus, Checking whether the write data queue is a pool if the input command is a memory write command and waiting until the pool is not the pool; Determining that the memory write address of the data requested by the memory write command is contiguous with the memory write address of the previous memory write command if it is determined that the pool is not full; Continuously writing data requested by the memory write command to the same item of the write data queue in which the data requested by the previous memory write command is stored; Validating an item of a write data queue in which data requested by a previous memory write command is stored, and writing the data requested by the memory write command to a next item of the write data queue if it is determined that the data is not continuous; And And writing data of a valid item among the items of the write data queue into a memory, and invalidating a corresponding item of the write data queue when memory writing is completed. The method of claim 13, And if the write data queue is empty, writing the data requested by the memory write command to a predetermined item of the write data queue, and terminating the memory write command. In the memory interface method of controlling the internal write data queue and read data buffer to write or read data to and from the memory when a memory write command or a memory read command is input from a specific memory access unit (MAU) through the system bus, Determining whether a memory read address included in the memory read command is in a write data queue when the input command is a memory read command; If it is determined that the specific item is in the write data queue and the item is in a valid state, reading data from the corresponding item in the write data queue, transferring the data to a system bus, and terminating a memory read command; Determining whether data for a memory read address included in the memory read command is stored in a read data buffer when it is determined that the write data queue is not in the write data queue; If the read data buffer is stored in the read data buffer and the read data buffer is in a valid state, transferring corresponding data of the read data buffer to a system bus and terminating a memory read command; And If the memory read address included in the memory read command is not in the write data queue and the read data buffer, reading data from the memory, storing the data in the read data buffer, transmitting the data to the system bus, and terminating the memory read command. And a memory read interface method. The method of claim 15, Validating the read data buffer if data read from the memory is stored in a read data buffer.