CN117056255B - Atomic operation device, method, equipment and medium - Google Patents
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- CN117056255B CN117056255B CN202311315140.3A CN202311315140A CN117056255B CN 117056255 B CN117056255 B CN 117056255B CN 202311315140 A CN202311315140 A CN 202311315140A CN 117056255 B CN117056255 B CN 117056255B
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- 230000004044 response Effects 0.000 claims description 13
- 238000003672 processing method Methods 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 9
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the disclosure provides an atomic operation device, method, device and medium, which belong to the field of data processing.
Description
Technical Field
The embodiment of the disclosure relates to the field of data processing, in particular to an atomic operation device, an atomic operation method, atomic operation equipment and an atomic operation medium.
Background
Atomic operation means that when a Thread (Thread) is to sequentially perform a "read-calculate-write" operation on the same memory variable, the "read-calculate-write" operation must be performed coherently and cannot be interrupted by any other operation.
Most of the prior art optimizes the whole architecture of the atomic operation multithreading access memory, but the basic implementation unit of the atomic operation is not optimized enough, so that the atomic operation efficiency is low, and the performance of a processor is reduced.
Disclosure of Invention
The invention aims to provide an atomic operation device, an atomic operation method, atomic operation equipment and an atomic operation medium, which are used for improving the atomic operation efficiency.
According to one aspect of the present disclosure, there is provided an atomic operation device, comprising,
a first judging module for judging normal operation and atomic operation,
a second judging module for judging whether the atomic operation is legal,
a buffer module, which comprises a plurality of FIFOs for buffering data corresponding to each channel of the bus protocol,
where the read request FIFO is set to non-empty read-as-you-go,
and the write-in data control module is used for controlling all bit data corresponding to one atomic operation to be written into the storage device at the same time.
In some embodiments, the apparatus further comprises an order preservation module to ensure that a desired order of operations is maintained for different types of operations at the same address.
In some embodiments, the bus protocol is an AXI protocol.
In some embodiments, the apparatus further comprises a calculation module for calculating data based on the atomic operation instruction.
According to another aspect of the present disclosure, there is provided an atomic operation processing method including:
based on the above-described atomic operation device,
an atomic operation request sent by the main device is received,
in response to an atomic operation request being legitimate, an operand of the legitimate atomic operation request is read from the storage device,
the calculation of the operands is performed based on the opcode of the atomic operation,
the calculated operands are rewritten back into the storage device,
and replying an atomic operation completion signal to the master device module.
In some embodiments, the method further comprises discarding the received data and reporting an error to the master device in response to the atomic operation request being illegal.
In some embodiments, the method further comprises reading an operand of the legitimate atomic operation request from the storage device, in particular, the read request FIFO issues immediately after receiving the read request.
In some embodiments, the method further comprises the operation code based on the atomic operation performs calculation of the operand, specifically, the data and the operand read back from the storage device are sent to the calculation module, and calculation is performed based on the atomic operation instruction.
In some embodiments, the method further includes rewriting the operand that is completed by the calculation back to the storage device, specifically, writing the result after the calculation into the corresponding FIFO, and writing the portion that does not participate in the calculation into the corresponding FIFO, while setting wstrb to 1 in its entirety.
In some embodiments, the method further comprises, in response to receiving the regular operation, comparing the regular operation with address information in each FIFO, suspending the regular operation request if the addresses are identical or partially overlapping, and processing the regular operation request after the atomic operation is completed.
The embodiment of the application also provides electronic equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the steps in the method in any embodiment by calling the computer program stored in the memory.
The embodiment of the application also provides a computer readable storage medium storing a computer program, which is characterized in that: the computer program, when executed by a processor, performs the steps of the method of any of the embodiments above.
The atomic operation processing method includes receiving an atomic operation request sent by a main device, responding to the legal atomic operation request, reading out an operand of the legal atomic operation request from a storage device, calculating the operand based on an operation code of the atomic operation, rewriting the calculated operand back to the storage device, and replying an atomic operation completion signal to a main device module.
Drawings
Fig. 1 is a schematic diagram of an atomic operation device according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a cache module according to an embodiment of the present application.
Fig. 3 is a schematic diagram of an atomic operation method according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings. The description of these embodiments is provided to assist understanding of the present invention, but is not intended to limit the present invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The terms "first" and "second" in this technical solution are merely references to the same or similar structures, or corresponding structures that perform similar functions, and are not an arrangement of the importance of these structures, nor are they ordered, or are they of a comparative size, or other meaning.
Example 1
Specifically, referring to fig. 1, an atomic operation device is provided in the present disclosure. Most of the prior art optimizes from the point of view of the overall architecture of the atomic operation multithreading access memory, but the basic implementation unit of the atomic operation is not optimized enough, and the embodiments focus on the design and optimization of an atomic operation basic unit.
The atomic operation device is internally provided with a first judging module which is used for judging conventional operation and atomic operation, wherein memory addresses which are possibly accessed by the conventional operation and the atomic operation are the same, but the atomic operation usually takes longer time than the conventional operation, and different control modes are needed for different operation types; and the second judging module is used for judging whether the atomic operation is legal or not. The atomic built-in operation buffer module comprises a plurality of FIFOs and is used for buffering data corresponding to each channel of a bus protocol. The caching module comprises a plurality of atomic operation FIFOs, which can cache a plurality of atomic operation requests and ensure the sequence of each operation, the number of the FIFOs can be set according to requirements, and it can be understood that in order to be capable of sequentially processing the plurality of atomic operation requests, one or more FIFOs can be correspondingly arranged for the bus protocol channel. As shown in fig. 2, which illustrates one embodiment of the present disclosure, taking the AMAB AXI protocol as an example, the protocol generally includes five channels, defined as follows: an AW write address channel, an AR read address channel, a W write data channel, an R read data channel and a B write response channel. As shown in FIG. 2, multiple FIFO implementations cooperate to handle multiple atomic operation requests. Wherein,
the pre_addr_fifo memory is used for storing the address of the atomic operation and the instruction, and if the instruction is detected to be illegal, namely the atomic operation request is illegal, the data is lost;
rq_fifo memory, read request FIFO, used to prepare the read request for transmission, and the address to be read; the rq_fifo sends a read request in principle that the read request is sent out immediately as long as the read request is available, and the aim of the read request is to save the time of the whole atomic operation; the atomic operation can be simplified as: reading from the storage device, modifying in the atomic operation unit, writing back to the storage (read-calculate-write or "RMW"), it takes a long time to read and write data from the storage device, conventionally: reading the first number of strokes and modifying, writing back to the storage device, and then reading the second number of strokes and modifying, and sequentially performing. In order to save time, the embodiment of the disclosure firstly reads out the operand of the request for reading the FIFO atomic operation in advance, calculates in the calculation unit, and then sequentially writes back the calculated data to the storage device;
addr_fifo memory for storing the address to be written;
a data_fifo memory for storing data desired to be written;
rtn _fifo memory for receiving and storing the read-back data (corresponding to the request issued by the AR) and the feedback given by the slave after writing (corresponding to the request issued by the AW)
The ALU arithmetic logic unit, namely a calculation module, is used for calculating operands, and the specific calculation rule is determined by an atomic operation instruction sent upstream; the atomic operation instruction may include exchange values after bitwise and, bitwise or, bitwise exclusive or, read-only, read-after-write, bitwise left-shift, bitwise right-shift, bitwise inversion, addition, subtraction, comparison, or other atomic operations, where embodiments of the disclosure are not limited;
wq fifo memory for caching the upcoming write address;
w fifo memory for buffering write data to be issued.
The atomic operation device also comprises a written data control module which is used for controlling all bit data corresponding to one atomic operation to be written into the storage device at the same time. The bit width (bit width) of the atomic operation is often smaller than that of the storage device, because of the attribute of the atomic operation, the 'RMW (read-modify-write)' operation is required to be performed on the storage device in the atomic operation basic processing unit, and because of the attribute of the minimum processing bit (bit) unit of the storage device, the storage device performs the 'RMW (read-modify-write)' operation on the written data smaller than the bit width once, so that the 'RMW (read-modify-write)' operation is required to be performed twice for one atomic operation, which is definitely time-consuming, thereby reducing the 'RMW (read-modify-write)' of the primary storage device and greatly shortening the time of the atomic operation and improving the efficiency of the atomic operation.
In atomic operation, not all bits of all data need to be operated, and the embodiment of the disclosure sets the write strobe signal (wstrb, for one operand, wstrb is used to indicate a valid data position) to be 1, replaces the part needing to be operated, and reserves the part without operation. For example, an atomic operation may only wish to modify 16 bits of a 256-bit data, and then the embodiment writes the modified 16 bits to the corresponding location, writes the portion that does not need to be modified to the original location as is, then sets wstrb to 1, and writes the modified 256-bit data to a storage device (e.g. DRAM, the type of storage device is not limited in this disclosure). This may avoid triggering read-modify-write operations of the memory controller, thereby further saving time.
Further, the atomic operation device also comprises an order keeping module for ensuring that the expected operation order is kept for different types of operations of the same address. If the address of the atomic operation and the address of the regular operation are the same, for example, the atomic operation with the same address is followed by the regular read operation with the same address, since the atomic operation is to perform a "read-calculate-write" operation, the regular read operation only needs to perform a read operation on the storage device, and it is seen that the processing time of the regular read operation is much shorter than the processing time of the atomic operation, which results in that the data read by the read operation is not the data after performing the atomic operation, and is not expected. This requires a persistence process for the same address access memory of the atomic operation and the normal operation, specifically, in order to ensure the same address persistence between the atomic operation and the normal operation, the embodiment reads the address information in wq_fifo, addr_fifo, rq_fifo, pre_addr_fifo, and compares with the normal operation read address transmitted from the host device. If the conventional read address transmitted by the master device is consistent with (or overlapped with) the addresses in the plurality of fifo, the address transmitted by the master device is blocked, so that the data of which the atomic operation calculation is completed is ensured to be transmitted to the memory, and then the access request with the same address transmitted by the master device is released.
Further, to cache multiple atomic operations, the present design designs fifo depth to 8. The depth can also be adjusted with the design requirements, with greater depth representing more atomic operations that can be stored.
Example two
Specifically, referring to fig. 3, an atomic operation method is provided in the present disclosure. Specifically, the atomic operation device according to the first embodiment,
step S1 receives an atomic operation request sent from a master device,
step S2, in response to the atomic operation request being legal, reads out the operands of the legal atomic operation request from the storage device,
step S3 performs operand calculation based on the operation code of the atomic operation,
step S4 rewrites the calculated operands back into the storage device,
step S5, an atomic operation completion signal is replied to the main equipment module.
With further reference to fig. 2, the implementation flow of the atomic operation of this embodiment is as follows:
the write address and atomic operation instruction of the aw channel firstly enter a pre_addr_fifo module; the atomic operation instruction is agreed in advance by software, if the atomic operation instruction received by the aw channel does not accord with the specification, the data of the aw channel and the w channel are all lost, and errors are reported to the main equipment through the B channel;
2. if the atomic operation instruction of pre_addr meets the specification, then the operand will be written to the w-channel. This operand is typically the part that is desired to be modified, and as to the rules how this part is modified, reference may be made to the corresponding specifications, for example, in one embodiment, a specific method of operation may be reference to the atomic operation of CUDA;
the address of the aw channel in the pre_addr_fifo will be written to rq_fifo, which will send a read request to the downstream module (e.g. storage device). The rq_fifo sends the read request in principle that the read request is sent immediately as long as the read request is needed, and the purpose of the read request is to save the time of the whole atomic operation, and the principle is described before and is not repeated here;
4. storing address information into addr_fifo, and storing data information into data_fifo, waiting for R channel read-back data, wherein the R channel read-back data corresponds to a read request sent by rq_fifo;
the R channel receives the read-back data, and the read-back data and the data in the data_fifo are sent to the ALU module to carry out corresponding operation, wherein the operation rule is determined by an atomic operation instruction sent upstream. Writing the result after operation into w_fifo, writing the part which does not need to participate in operation into w_fifo, and setting wstrb to 1 at the same time, wherein the aim of doing so is to avoid triggering read-modify-write of the storage controller, thereby further saving the whole time of atomic operation;
the write address in wq_fifo and the write data in w_fifo will be sent out simultaneously;
7. waiting for a write response of the B channel, and after the atomic operation unit receives the write response, transmitting the response signal to the upstream (e.g., master device), at which time the work inside the atomic operation unit is completed.
Example III
Correspondingly, the embodiment of the application also provides electronic equipment which can be a terminal or a server. As shown in fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
The electronic device 400 includes a processor 401 having one or more processing cores, a memory 402 having one or more computer readable storage media, and a computer program stored on the memory 402 and executable on the processor. The processor 401 is electrically connected to the memory 402. It will be appreciated by those skilled in the art that the electronic device structure shown in the figures is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
The processor 401 is a control center of the electronic device 400, connects various parts of the entire electronic device 400 using various interfaces and lines, and performs various functions of the electronic device 400 and processes data by running or loading software programs (computer programs) and/or units stored in the memory 402, and calling data stored in the memory 402.
In the embodiment of the present application, the processor 401 in the electronic device 400 loads the instructions corresponding to the processes of one or more application programs into the memory 402 according to the following steps, and the processor 401 executes the application programs stored in the memory 402, so as to implement various functions:
an atomic operation request sent by the main device is received,
in response to an atomic operation request being legitimate, an operand of the legitimate atomic operation request is read from the storage device,
the calculation of the operands is performed based on the opcode of the atomic operation,
the calculated operands are rewritten back into the storage device,
and replying an atomic operation completion signal to the master device module.
The specific implementation of each operation may refer to the foregoing embodiments, and will not be repeated herein.
Optionally, as shown in fig. 4, the electronic device 400 further includes: an atomic operation device 403, a communication module 404, an input unit 405, and a power supply 406. The processor 401 is electrically connected to the atomic operation device 403, the communication module 404, the input unit 405 and the power supply 406, respectively. Those skilled in the art will appreciate that the electronic device structure shown in fig. 4 is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.
Atomic operation device 403 may be used to implement the processing of atomic operation requests.
The communication module 404 may be used to communicate with other devices.
The input unit 405 may be used to receive input numbers, character information, or user characteristic information (e.g., fingerprint, iris, facial information, etc.), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control.
The power supply 406 is used to power the various components of the electronic device 400. Alternatively, the power supply 406 may be logically connected to the processor 401 through a power management system, so as to implement functions of managing charging, discharging, and power consumption management through the power management system. The power supply 406 may also include one or more of any components, such as a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator, and the like.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
Example IV
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.
To this end, embodiments of the present application provide a computer readable storage medium having stored therein a plurality of computer programs that can be loaded by a processor to perform the steps of a method for resource sharing in convolution computation provided by embodiments of the present application. For example, the computer program may perform the steps of:
an atomic operation request sent by the main device is received,
in response to an atomic operation request being legitimate, an operand of the legitimate atomic operation request is read from the storage device,
the calculation of the operands is performed based on the opcode of the atomic operation,
the calculated operands are rewritten back into the storage device,
and replying an atomic operation completion signal to the master device module.
The specific implementation of each operation above may be referred to the previous embodiments, and will not be described herein.
Wherein the computer-readable storage medium may comprise: read Only Memory (ROM), random access Memory (RAM, randomAccess Memory), magnetic disk or optical disk, and the like.
The steps in any of the atomic operation processing methods provided in the embodiments of the present application may be executed by the computer program stored in the storage medium, so that the beneficial effects that any of the atomic operation processing methods provided in the embodiments of the present application may be achieved, which are described in detail in the previous embodiments and are not repeated herein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, and yet fall within the scope of the invention.
Claims (11)
1. An atomic operation device, comprising,
a first judging module for judging normal operation and atomic operation,
a second judging module for judging whether the atomic operation is legal,
a buffer module, which comprises a plurality of FIFOs for buffering data corresponding to each channel of the bus protocol,
where the read request FIFO is set to non-empty read-as-you-go,
the write-in data control module is used for controlling all bit data corresponding to one atomic operation to be written into the storage device at the same time, specifically, for one operand corresponding to the atomic operation, only the data bits expected to be modified by the atomic operation are modified, the part which does not need to be modified is written into the original position in an intact manner, then wstrb is set to be 1, and all the data bits are written into the storage device.
2. The apparatus of claim 1, further comprising,
and the order keeping module is used for ensuring that the expected operation order is kept for different types of operations of the same address.
3. The apparatus of claim 1, further comprising,
the bus protocol is AXI protocol.
4. The apparatus of claim 1, further comprising,
and the calculation module is used for calculating the data based on the atomic operation instruction.
5. An atomic operation processing method is characterized in that,
an atomic operation device according to any one of claim 1 to 4, comprising,
an atomic operation request sent by the main device is received,
in response to an atomic operation request being legitimate, an operand of the legitimate atomic operation request is read from the storage device,
the calculation of the operands is performed based on the opcode of the atomic operation,
the calculated operands are rewritten back into the storage device,
an atomic operation completion signal is returned to the master device module,
and re-writing the calculated operand back to the storage device, namely, for one operand corresponding to the atomic operation, only modifying the data bits expected to be modified by the atomic operation, directly writing the part which does not need to be modified into the original position, setting wstrb to be 1, and writing all the data bits into the storage device.
6. The method of claim 5, wherein the method further comprises:
and discarding the received data and reporting an error to the master device in response to the illegal atomic operation request.
7. The method of claim 5, wherein the method further comprises:
the operand of the legal atomic operation request is read out from the storage device, specifically, the read request FIFO sends out immediately after receiving the read request.
8. The method of claim 5, wherein the method further comprises:
the operation code based on the atomic operation performs operand calculation, specifically, data and operands read back from the storage device are sent to a calculation module, and calculation is performed based on an atomic operation instruction.
9. The method of claim 5, wherein the method further comprises:
in response to receiving the normal operation, comparing the normal operation with address information in each FIFO, suspending the normal operation request if the addresses are consistent or partially overlapped, and processing the normal operation request after the atomic operation is completed.
10. An electronic device, characterized in that: comprising a memory storing executable program code and a processor coupled to the memory; wherein the processor invokes executable program code stored in the memory to perform the method of any of claims 5-9.
11. A computer-readable storage medium storing a computer program, characterized in that: the computer program, when executed by a processor, performs the method of any of claims 5-9.
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