CN111984562A - Method for burst access control of register, electronic device and storage medium - Google Patents
Method for burst access control of register, electronic device and storage medium Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention provides a method for controlling burst access of a register, electronic equipment and a storage medium, wherein the method comprises the following steps: s1, receiving a read request and a write request sent by the master device by the multi-channel; s2, converting the currently received read request or write request through the sending interface protocol time sequence, and sending the read request and the write request to the slave equipment through the same data sending channel; s3, converting the response data fed back by the slave device corresponding to the read request or the write request through the receiving interface protocol time sequence, so as to feed back the response data of the slave device through the same data return channel; the response data comprises read data information and read state information which are fed back corresponding to the read request, and write state information which is fed back corresponding to the write request; and S4, analyzing the receiving interface protocol time sequence, and feeding back response data corresponding to the read request and response data corresponding to the write request to the master device through different data return channels respectively. The invention simplifies the control logic and realizes the transmission of data in a pipeline mode.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and mainly relates to a method and a device for burst access control of a register and a storage medium.
Background
In ASIC design, a large number of entries or registers which can configure or record the running state of a chip exist on a slave device; the main device (which may be an external or an internal main device, such as a CPU, etc.) connected to the ASIC needs to read and write the table entries or registers; this channel of reading and writing is called a register access interface. As the functions supported by the ASIC become more and more, the logic design becomes more and more complex, and more entries and registers need to be accessed by the host device; how to improve the processing performance of the register access interface, it becomes more and more important to improve the access efficiency of the master device to the table entries and registers on the slave device.
The factors influencing the efficiency of the main device accessing the table entries and the registers mainly include whether the operation steps of the main device reading and writing the table entries or the registers are simple or not and the processing performance of the register access interface. In the prior art, the following two schemes are adopted to improve the processing performance of the register access interface.
In the first scheme, a Local Bus (also called CPU Bus) Bus interface protocol in a chip is used as a register access interface protocol, and a master device directly operates the Bus interface to realize read-write access to a slave device; in the second scheme, an Advanced Microcontroller Bus Architecture (Bus on chip protocol cluster proposed by ARM) of ARM company is adopted, and Bus interface protocols including axi (Advanced eXtensible interface), ahb (Advanced High Performance Bus), apb (Advanced Performance Bus) and the like) realize an access interface between the master device and the slave device, and the master device operates the AMBA Bus interface to realize read-write access to the slave device.
LocalBus is mainly used for a data access operation interface between a CPU and other external equipment at the beginning of design, and has a plurality of varieties of designs; when used for on-chip design, a common interface design includes request signal lines such as an address line, a write data line, a read/write flag line, and a read/write enable line, and a return result signal line such as a return valid flag line, a return read data line, and a return result status flag line. The operation process is as follows: the main equipment sends the read-write request to the request signal line; and after the slave equipment finishes processing, the result is also sent to the corresponding return result signal line, and then the master equipment acquires the return result.
However, the LocalBus design idea is used for low-speed processing, so that the protocol can only perform read or write operations on data at one address at a time during operation, which is called single data operation; the main equipment is required to send a new operation request after receiving the previous operation result, and the assembly line processing cannot be carried out, so the processing performance is low; part of the LocalBus also requires that the slave device must respond within a fixed time, with a large limitation on the design of the slave device.
The second solution in the prior art is the AMBA bus interface protocol defined by ARM corporation after ARM CPU is gradually started in the embedded field. The invention takes the function of realizing register access by the high-performance bus interface protocol AXI in the AMBA bus protocol cluster as an example for specific introduction. As shown in fig. 1, 5 channels of write address, write data, write response, read address, and read data are defined in the AXI protocol; the AXI write address channel is used for the master equipment to send information such as a write address, the number of write data, the type of write operation and the like; the device comprises an AXI (advanced extensible interface) data writing channel, a data writing unit and a data reading unit, wherein the AXI data writing channel is used for sending information such as data writing, a data writing byte valid mark and a data writing last data valid mark by a master device; an AXI write response channel for returning write operation result information from the device; the AXI read address channel is used for the main equipment to send information such as read addresses, the number of read data, the type of read operation and the like; and the AXI read data channel is used for returning information such as read data and read operation state from the equipment. The master device and the slave device independently perform handshake processing on each channel, and specific data sampling is finished when both the master device and the slave device are ready; different channels are independent from each other and can be subjected to pipeline processing; and meanwhile, a plurality of data are operated at one time, and the design greatly improves the efficiency of data transmission.
The AXI protocol is more efficient in processing data, but the cost of implementing the protocol is also very large; the design of five relatively independent channels greatly increases the logic complexity of the slave device; because the table entries and registers on the slave device are all dispersed in a plurality of sub-modules, correspondingly, each sub-module needs to have a group of register access interfaces; if the AXI protocol is used directly as the register interface, each submodule has a more complex interface control logic. In addition, AXI multi-channel designs can also cause the problem of inconsistent access request order and returned result order, which is unacceptable for ASICs.
The AXI bus protocol is designed according to the characteristics of a CPU bus and is suitable for a flat connection structure, and entries and registers in an ASIC exist in a plurality of sub-modules, which generally have a multi-level structure. Forcing the logic for access using AXI inevitably adds too much conversion control logic and is not reimbursed for ASIC chip development. In addition, in fact, the main application scenario of the AXI protocol is in the interface design of a CPU and a cache (such as a DDR or an internal high-speed memory); the access to the entries and registers of the slave in the ASIC is not directly available.
Disclosure of Invention
To solve the above technical problems, an object of the present invention is to provide a method, an electronic device, and a storage medium for burst access control of a register.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for controlling burst access to a register, the method including: s1, receiving a read request and a write request sent by the master device by the multi-channel;
s2, converting the currently received read request or write request through the sending interface protocol time sequence, so as to send the read request and the write request to the slave equipment through the same data sending channel;
s3, converting the response data fed back by the slave device corresponding to the read request or the write request through the receiving interface protocol time sequence, so as to feed back the response data of the slave device through the same data return channel; the response data comprises read data information and read state information which correspond to the read request feedback, and write state information which corresponds to the write request feedback;
and S4, analyzing the receiving interface protocol time sequence, and feeding back the response data corresponding to the read request and the response data corresponding to the write request to the main equipment through different data return channels respectively.
As a further improvement of an embodiment of the present invention, the method further comprises:
receiving a write request by adopting an AXI write address channel and an AXI write data channel of an AXI interface protocol;
receiving a read request by adopting an AXI read address channel of an AXI interface protocol;
feeding back and analyzing the write state information obtained by the time sequence of the receiving interface by adopting an AXI write response channel of an AXI interface protocol;
and feeding back and analyzing the read data information and the read state information obtained by the time sequence of the receiving interface by adopting an AXI read data channel of an AXI interface protocol.
As a further improvement of an embodiment of the present invention, between step S1 and step S2, the method further includes:
m1, storing the write request and the read request received by different channels respectively;
m2, arbitrating the read request and the write request so that only one of them is converted in time sequence by the interface protocol at the same time.
As a further improvement of an embodiment of the present invention, step M1 includes:
respectively writing the state signals related to the write request, the data signals related to the write request and the state signals related to the read request which are received through different channels into different FIFOs; the write request related status signals include: write address, write data length, write data width; the write request related data signals include: writing data, a valid writing section mark and a valid mark of the last data of the current writing data; the read request related status signals include: reading address, reading data length and reading data width;
when the FIFOs corresponding to the status signals relevant to the write request and the data signals relevant to the write request have data, extracting the write request from the corresponding FIFOs and generating arbitration status marks for the write request; when the FIFO corresponding to the status signal related to the read request has data, extracting the read request from the corresponding FIFO and generating an arbitration status flag for the read request;
step M2 includes: and arbitrating the read request and the write request according to arbitration status flags carried by the read request and the write request so as to convert the time sequence of only one of the read request and the write request through the interface protocol at the same time.
As a further improvement of an embodiment of the present invention, the transmission interface protocol timing sequence includes:
a reqValid signal, which is used to mark whether the current request is valid or not when a read request or a write request is received;
a reqRead signal for marking whether a read operation or a write operation is currently selected when a read request or a write request is received;
the reqCmd signal identifies the type of the transferred data at a first moment on the premise that the reqValid signal is valid, and each moment represents whether the current access is valid or whether the current access is the last data to be transferred from a second moment;
the data processing device comprises a reqAddrData signal and a data processing unit, wherein the reqAddrData signal transmits an initial address of slave equipment which needs to be accessed by a read request or a write request at a first moment on the premise that a reqValid signal is effective; if the transmitted write requests are from the second moment, sequentially transmitting the write data at each moment; if a read request is passed, any data may be transferred.
As a further improvement of an embodiment of the present invention, the sending interface protocol timing sequence further includes: a reqUserInfo signal, which is used for function extension.
As a further improvement of an embodiment of the present invention, the receiving interface protocol timing sequence includes:
an ackValid signal for indicating whether currently fed back response data is valid;
an ackError signal for identifying whether an error is contained in the reply data;
ackData signals, which are used to convey specific response data or to transmit error codes in the event of an error in the response data.
As a further improvement of an embodiment of the present invention, the receiving interface protocol timing sequence further includes:
an ackUserInfo signal, which is used for functional extension.
As a further improvement of an embodiment of the present invention, the method further comprises: connecting the interfaces of each sub-module of the slave equipment in a cascade mode;
when the slave device receives a request command through the same data transmission channel, wherein the request command is the read request or the write request, each submodule in the slave device is sequentially prompted to be matched and confirmed with an access address in the request command according to the cascade order,
if the addresses are the same, performing request command response in the current sub-module to generate response data; after the response data is formed, the request command and the response data are synchronously sent to the next submodule;
if the addresses are different, directly sending the data received by the current sub-module to the next sub-module;
and if the current submodule is the last submodule, only the response data is fed back through the same data channel.
As a further improvement of an embodiment of the present invention, the method further comprises: making star connection for the interface of each sub-module of the slave device;
adding a sequence identifier to each request command, wherein the request command is the read request or the write request;
when the slave equipment receives a request command through the same data transmission channel, searching a sub-module matched with the address according to the access address of the request command;
request command response is carried out in the address matching sub-module to generate response data, and meanwhile, the same sequence identification as the request command is added to each response data;
and outputting each response data in sequence in the same data channel according to the generation sequence of the sequence identifier in the request command.
In order to achieve one of the above objects, an embodiment of the present invention provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program operable on the processor, and the processor executes the computer program to implement the steps in the register burst access control method.
In order to achieve one of the above objects, an embodiment of the present invention provides a computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the method for register burst access control as described above.
Compared with the prior art, the invention has the beneficial effects that: according to the register burst access control method, the electronic device and the storage medium, the transmission interface protocol time sequence and the receiving interface protocol time sequence are added between the master device and the slave device, the control logic is simplified, data are transmitted in a pipeline mode, and the execution efficiency is improved.
Drawings
Fig. 1 is a schematic diagram of an AXI protocol interface proposed in the background of the invention;
FIG. 2 is a flow chart of a register burst access control method provided by the present invention;
FIG. 3 is a diagram of a transmit interface protocol timing signal provided by one embodiment of the present invention;
fig. 4 and 5 are schematic diagrams illustrating connection modes of sub-modules in a slave device according to different embodiments of the present invention; (ii) a
FIG. 6 is a diagram of a receive interface protocol timing signal provided in accordance with one embodiment of the present invention;
fig. 7 is a block diagram of a register burst access control device provided by the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
The invention adds a transmitting interface protocol time sequence and a receiving interface protocol time sequence between the main device and the slave device, wherein the interface protocol time sequence is a register access interface protocol supporting burst read-write operation, converts an access request from a main device high-speed bus into the protocol through a section of simple and easy-to-realize logic, and then connects the protocol with each submodule in an ASIC (application specific integrated Circuit), realizes unified and simple register logic in each submodule, realizes the control of table items and registers in each submodule, completes the read-write request operation of the main device, and returns a result.
As shown in fig. 2, a register burst access control method according to an embodiment of the present invention includes:
s1, receiving a read request and a write request sent by the master device by a multi-channel;
s2, converting the currently received read request or write request through the sending interface protocol time sequence, so as to send the read request and the write request to the slave equipment through the same data sending channel;
s3, converting the response data fed back by the slave device corresponding to the read request or the write request through the receiving interface protocol time sequence, so as to feed back the response data of the slave device through the same data return channel; the response data comprises read data information and read state information which correspond to the read request feedback, and write state information which corresponds to the write request feedback;
and S4, analyzing the receiving interface protocol time sequence, and feeding back the response data corresponding to the read request and the response data corresponding to the write request to the main equipment through different data return channels respectively.
In the preferred embodiment of the present invention, for step S1 and step S4, in order to accelerate the data processing process, the data communication between the master device and the slave device is pipelined; the request sent by the master device to the slave device comprises a read request and a write request, and the response data fed back by the slave device to the master device comprises read data information and read state information corresponding to the read request and write state information corresponding to the write data request; further, the master device sends a read request and a write request through multiple channels; meanwhile, receiving corresponding response data through multiple channels; the slave device internally comprises a plurality of submodules, so that in order to simplify the processing logic of the slave device, a read request and a write request are received through only one channel, and corresponding response data are fed back through only one channel.
In a preferred embodiment of the present invention, the main channel output port and the feedback receiving port both use an AXI interface protocol, which is characterized in that as shown in fig. 1 of the background art, the read-write operation is performed by 5 independent channels; thus, multi-channel output and multi-channel feedback receiving are realized; specifically, the channel corresponding to the port of the master device includes: AXI write address channel, AXI write data channel, AXI read address channel, AXI write response channel, and AXI read data channel feedback. Receiving a write request by an AXI write address channel and an AXI write data channel of an AXI interface protocol; receiving a read request by adopting an AXI read address channel of an AXI interface protocol; feeding back and analyzing the write state information obtained by the time sequence of the receiving interface by adopting an AXI write response channel of an AXI interface protocol; and feeding back and analyzing the read data information and the read state information obtained by the time sequence of the receiving interface by adopting an AXI read data channel of an AXI interface protocol.
Preferably, between step S1 and step S2, the read request and the write request transmitted by the master device through the 3-channel need to be converted to the same channel and sent to the slave device; specifically, the method further comprises:
m1, storing the write request and the read request received by different channels respectively;
m2, arbitrating the read request and the write request so that only one of them is converted in time sequence by the interface protocol at the same time.
For step M1, the method specifically includes: respectively writing the state signals related to the write request, the data signals related to the write request and the state signals related to the read request which are received through different channels into different FIFOs; the write request related status signals include: information such as write address, write data length, write data width, etc.; the write request related data signals include: writing data, a valid writing section mark, a valid mark of the last data of the current writing data and other information; the read request related status signals include: read address, read data length, read data width, etc.
When the FIFOs corresponding to the status signals relevant to the write request and the data signals relevant to the write request have data, extracting the write request from the corresponding FIFOs and generating arbitration status marks for the write request; when the FIFO corresponding to the status signal related to the read request has data, extracting the read request from the corresponding FIFO and generating an arbitration status flag for the read request;
for step M2, it specifically includes: and arbitrating the read request and the write request according to arbitration status flags carried by the read request and the write request so as to convert the time sequence of only one of the read request and the write request through the interface protocol at the same time.
For step M2, because the read-write request on the AXI bus is triggered by mutually independent channels, there may be a case where the read request and the write request are both present; in the invention, only one set of interfaces is provided for the table entries and the registers on the slave device, and only one operation can be executed simultaneously by reading and writing; arbitration selection between read and write requests is required when generating register access requests.
Specifically, the read-write state information of the read request and the write request is received, and according to a preset rule, for example: the equal proportion cycle scheduling rule selects and executes from the effective read request and write request; if the write operation is selected to be executed, the write request information is sent to a register access interface of a lower level; if the read operation is selected, the read request information is sent to the register access interface of the lower level.
For step S3, the adopted transmission interface protocol timing sequence includes:
a reqValid signal, which is used to mark whether the current request is valid or not when a read request or a write request is received; it can be represented by binary digits "0" "1", such as: the flag is "0" to indicate invalid, and the flag is "1" to indicate valid.
A reqRead signal for marking whether a read operation or a write operation is currently selected when a read request or a write request is received; it can be represented by binary digits "0" "1", such as: a flag of "0" indicates a write operation, and a flag of "1" indicates a read operation.
The reqCmd signal identifies the type of the transferred data at a first moment on the premise that the reqValid signal is valid, and each moment represents whether the current access is valid or whether the current access is the last data to be transferred from a second moment; specifically, the state of the reqCmd signal in the register interface timing sequence at the 1 st moment after reqValid is generated according to the length and type of data included in the current read request or write request, for example: only one datum is currently accessed, reqCmd may be set to "0" to indicate; if multiple data are to be accessed continuously, reqCmd may be set to "1" for indication; starting from the 2 nd moment, indicating whether the current access is effective or not or whether the current access is the last data by using reqCmd; of course, the representation of the various states is also represented in binary values, so that the reqCmd signal can control the number of data in a register burst access; burst access operation with variable length is supported, and the flow control requirement of a post-stage module can be responded; the flexibility of the register access interface is greatly improved;
the data processing device comprises a reqAddrData signal and a data processing unit, wherein the reqAddrData signal transmits an initial address of a slave device which needs to be accessed by a read request or a write request at a first moment on the premise that a reqValid signal is effective; if the transmitted write requests are from the second moment, sequentially transmitting the write data at each moment; if a read request is passed, any data may be transferred. In the invention, the address and data lines are the most occupied signal lines in the register access, so that when the reqAddrData signal is designed, the writing address and the writing data are combined into one group of signal lines, and the number of the signal lines needing to be transmitted on the whole chip can be greatly saved.
In addition, it should be noted that, in the process of extracting the start address of access from the received data and converting the start address into the start address of the table entry or the register in the slave device, the extracted start address and the start address of the slave device to be accessed may be in one-to-one correspondence, or may be converted by querying an address mapping table. The reqAddrData signal is used to transmit the start address in the first time after the reqValid signal is valid; if the write operation is executed, the write data corresponding to the write request is extracted, and the write data is transmitted on reqaddrData by matching with a reqCmd signal from the 2 nd moment after the reqValid signal is valid.
Preferably, there will be some other status information in the AXI protocol, some of which may be used depending on the design of the slave device; thus, the transmission interface protocol timing sequence of the present invention further includes: a reqUserInfo signal, the reqUserInfo signal for functional expansion; this signal is set as required and can be optionally omitted in most basic register access applications.
For ease of understanding, the present invention is described with reference to a specific example.
Referring to fig. 3, the time T _1 represents the 1 st time after the reqValid signal is valid; the reqCmd signal at time T _1 represents the current access type; reqAddrData represents the starting address of the current access; the reqRead signal indicates whether the current access is a read or write operation from the time T _ 1; reqUserInfo is then set as needed, for example: the setting indicates whether the current operation is an atomic operation (referring to the entire operation process including a plurality of consecutive read or write operations), and so on.
The start reqCmd signal and reqAddrData signal at time T _2 indicate whether the current access is continuously valid and whether the current write data is valid.
At time T _3, the reqCmd signal is invalid indicating that access is suspended and the slave device may ignore the operation at time T _ 3.
At time T _ N, the reqCmd signal indicates the last data currently accessed (write data L is the last 1 write data), and after time T _ N, the access request sent to the slave has been completely sent.
As can be seen from the above example: the reqValid signal represents a complete register access request process, and needs to be kept valid in the whole access request process; the reqRead signal indicates whether the current register access is a read or write operation and needs to remain unchanged throughout the access request. The reqCmd signal indicates the current access type, such as a single data operation or a burst operation of multiple data, at time 1 when the reqValid signal is active; indicating whether the access is valid and is the last data in the valid time of the subsequent reqValid signal; the signal can be set to be in an invalid state, and the signal is used for the situation that a post-stage module is not in time to process and needs to perform flow control; the reqAddrData signal represents the initial address of the current access at the 1 st moment when the reqValid signal is valid, and subsequently, the write data is transmitted when the reqCmd signal is valid and the current write operation is performed; the reqUserInfo signal is used for function expansion, special control can be added on the signal line according to implementation requirements in use so as to meet different application requirements, and the signal can be ignored in basic application.
Further, after the register access interface request (read request or write request) is sent, a new request can be initiated at the time T _ N +1 without waiting for the result to come back, that is, by adopting a pipeline processing mode.
Preferably, before the time-series converted read request and write request are sent to the slave device, the method further includes: the access sequence of each sub-module (register) in the slave device is set, and the access sequence of each sub-module can be controlled according to the time sequence or the dynamic disorder.
In one embodiment of the present invention, the access sequence of each sub-module in the slave device is strictly accessed according to the time sequence, specifically, the interfaces of each sub-module of the slave device are connected in a cascade manner; as shown in fig. 4, the number of slave submodules in the slave device is N, correspondingly, the submodule 1 is connected to the data transmission channel, each submodule in the slave device is sequentially connected according to the serial number, and the response data is output through the last submodule N in the slave device.
Specifically, when the slave device receives a request command through the same data transmission channel, the request command is the read request or the write request, each sub-module in the slave device is sequentially prompted to match and confirm with an access address in the request command according to the cascade order, and if the addresses are the same, a request command response is performed in the current sub-module to generate response data; after the response data is formed, the request command and the response data are synchronously sent to the next submodule; if the addresses are different, directly sending the data received by the current sub-module to the next sub-module; and if the current submodule is the last submodule, only the response data is fed back through the same data channel.
In the embodiment, after a read request or a write request enters a slave device port, address matching must be performed in sequence according to the connection sequence of the sub-modules, if the read request or the write request is the same as the slave device port, read and write operations are performed, and the fed-back response data and the received read and write requests are sent to the subsequent sub-modules together, and if the read request or the write request is different from the received read and write requests, the read and write requests are only transmitted to the next sub-module without being changed, until the last sub-module feeds back the response data to the slave device.
In the embodiment, the access requests are transmitted in each submodule of the whole slave device according to the same line, and the feedback response data is necessarily output in sequence, so that the number of wires on a chip can be greatly reduced; the access mode correspondingly increases the return time of each access, but for continuous access, the time of the first access is prolonged, and the processing efficiency is not influenced when continuous access is provided subsequently.
In another mode of the invention, dynamic out-of-order control can be set for each submodule, specifically, the interface of each submodule of the slave device is in star connection; as shown in fig. 5, the number of slave submodules in the slave device is N, correspondingly, each submodule in the slave device is arranged in parallel, according to the address of the submodule, the data transmission channel corresponds to the access interface of each submodule, and the data output channel corresponds to the output interface of each submodule in the slave device.
Specifically, a sequence identifier is added to each request command, where the request command is the read request or the write request; when the slave equipment receives a request command through the same data transmission channel, searching a sub-module matched with the address according to the access address of the request command; request command response is carried out in the address matching sub-module to generate response data, and meanwhile, the same sequence identification as the request command is added to each response data; and outputting each response data in sequence in the same data channel according to the generation sequence of the sequence identifier in the request command.
In this embodiment, since the response time of each sub-module is different, the output result may not be consistent with the time sequence of the received access request, so that the reqUserInfo signal is used to add a sequence identifier to the access request, and correspondingly, the ackUserInfo signal is correspondingly added to the protocol timing sequence of the receiving interface for outputting according to the sequence of the signal identifier when the response data is identified. If the time for partial sub-modules in the slave device to respond to the register access request is long, the access operation of other normal sub-modules cannot be influenced by the current sub-module which requests feedback, and the register response efficiency of the whole slave device is improved.
With respect to step S4, after receiving a read request or a write request from the device, the slave device completes the operation according to the specified command and returns the result, and accordingly, the write operation only returns the write status information, and the read data also returns the read data information.
Correspondingly, the protocol time sequence of the receiving interface adopted by the invention comprises the following steps:
an ackValid signal for indicating whether currently fed back response data is valid;
an ackError signal for identifying whether an error is included in the response data when the ackValid signal is asserted;
an ackData signal, which is used to convey specific response data when the ackValid signal is active or to transmit error codes when the response data is erroneous.
Preferably, the receiving interface protocol timing further comprises: an ackUserInfo signal, the ackUserInfo signal for functional expansion; in the above example, the signal is used to transmit the sequence identification.
For ease of understanding, the present invention is described with reference to a specific example.
Referring to fig. 6, time T _1 represents the 1 st time after the ackValid signal is valid, and the operation result of the 1 st data is returned within time T _ 1; taking response data corresponding to the read request as an example, if an error exists, an error state is marked through an ackError signal, and the error state is specifically an error or no error exists; if the ackValid signal is valid and the ackError signal indicates that no error exists, transmitting the read data through the ackData signal, and if the ackValid signal is valid and the ackError signal indicates that an error exists, transmitting specific error codes through the ackData signal; further, when the sub-modules are connected in a cascade manner, the ackUserInfo signal is not used and can be directly ignored or not set, and when the sub-modules are connected in a star manner, the ackUserInfo signal is used for transmitting the sequence identifier.
As can be seen from the above example: the ackValid signal indicates that the current return result is valid, and other return signals can be sampled only when the signal is in a valid state; the ackError signal is used for indicating whether the returned result contains errors or not; the ackData signal is used for representing return data, is used for transmitting the returned read data for normal read operation, and can be used for transmitting error codes for the case of errors in the read or write operation, so that the error state can be conveniently debugged by the main equipment; the ackUserInfo signal is used for functional expansion and may be augmented with a special return status signal as needed, which is negligible in basic applications.
It should be noted that, in the timing diagrams shown in fig. 3 and fig. 6, for convenience of observation, each signal corresponding to each moment is identified by a specific identifier in a text, and in practical applications, all identifiers are represented by binary digits, which is not further described herein. In addition, the english identifiers of the various timing signals included in the transmission interface protocol timing and the reception interface protocol timing do not have any meaning, and each english identifier is only used for distinguishing each timing signal.
Furthermore, the response data is divided into two groups of results according to reading and writing, and the results are fed back to the main equipment through two channels.
Further, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a computer program executable on the processor, and the processor executes the computer program to implement the steps in the register burst access control method as described above.
Further, an embodiment of the present invention provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps in the register burst access control method as described above.
Referring to fig. 7, a block diagram of a register burst access control apparatus according to an embodiment of the present invention is shown; the device comprises: a master device 100; a request receiving module, a request arbitration module 300, an access interface timing generation module 400, an access request distribution control module 500 and a slave device 600, which sequentially process read and write requests of the master device 100; and a feedback data collection module 700 and a feedback data processing module 800 which sequentially process the response data of the slave device 600.
The master device 100 is configured to send a read-write request to the slave device 600; the request receiving module comprises a read request receiving module 201 and a write request receiving module 202; the read request receiving module 201 is configured to receive a read request of the host device 100, the write request receiving module 202 is configured to receive a write request of the host device 100, the request receiving module is specifically configured to implement step S1 and step M1, the request arbitration module 300 is configured to select one of the read request and the write request at the same time to execute, and is specifically configured to implement step M2; the access interface timing sequence generating module 400 is configured to convert a received read request or write request into a transmission interface protocol timing sequence, and is specifically configured to implement step S2, where the access request distribution control module 500 is configured to search a sub-module that receives a current read request or write request according to an instruction receiving rule of each sub-module in the slave device 600, and distribute the read request or write request to the searched sub-module through the same transmission channel; specifically, the slave device 600 is configured to configure relationships between sub-modules of the slave device and interface connection modes between the slave device and its upper module and lower module; the slave device 600 includes N sub-modules, each of which is configured to execute a read request or a write request sent by the master device 100 according to the transmission interface protocol timing sequence, and feed back response data to the master device 500 according to the read request or the write request; the feedback data collection module 700 is configured to convert the received feedback response data into a receiving interface protocol timing sequence, and is specifically configured to implement step S3; the feedback data processing module 800 is configured to analyze the receiving interface protocol timing sequence, and feed back the result to the master device 100 through the corresponding transmission channel, and is specifically configured to implement step S4.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the system described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
In summary, the register burst access control method, the electronic device, and the storage medium of the present invention can use simpler processing logic, fewer signal lines, and achieve higher working efficiency when performing read/write access to the table entry and the register on the slave device of the ASIC by adding the transmitting interface protocol timing sequence and the receiving interface protocol timing sequence between the master device and the slave device; the problem that the efficiency of on-chip Local Bus and APB Bus is too low and the problem that control logic of high-speed Bus such as AXI is too complex are solved; meanwhile, the definition of the UserInfo signal line also provides a flexible function expansion interface for use, so that the upgrading of the interface function is convenient.
The above described system embodiments are merely illustrative, wherein the modules described as separate parts may or may not be physically separate, and the parts shown as modules are logic modules, i.e. may be located in one module in the chip logic, or may be distributed to a plurality of data processing modules in the chip. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (12)
1. A method of register burst access control, the method comprising:
s1, receiving a read request and a write request sent by the master device by the multi-channel;
s2, converting the currently received read request or write request through the sending interface protocol time sequence, so as to send the read request and the write request to the slave equipment through the same data sending channel;
s3, converting the response data fed back by the slave device corresponding to the read request or the write request through the receiving interface protocol time sequence, so as to feed back the response data of the slave device through the same data return channel; the response data comprises read data information and read state information which correspond to the read request feedback, and write state information which corresponds to the write request feedback;
and S4, analyzing the receiving interface protocol time sequence, and feeding back the response data corresponding to the read request and the response data corresponding to the write request to the main equipment through different data return channels respectively.
2. The register burst access control method of claim 1, further comprising:
receiving a write request by adopting an AXI write address channel and an AXI write data channel of an AXI interface protocol;
receiving a read request by adopting an AXI read address channel of an AXI interface protocol;
feeding back and analyzing the write state information obtained by the time sequence of the receiving interface by adopting an AXI write response channel of an AXI interface protocol;
and feeding back and analyzing the read data information and the read state information obtained by the time sequence of the receiving interface by adopting an AXI read data channel of an AXI interface protocol.
3. The register burst access control method of claim 1, wherein between step S1 and step S2, the method further comprises:
m1, storing the write request and the read request received by different channels respectively;
m2, arbitrating the read request and the write request so that only one of them is converted in time sequence by the interface protocol at the same time.
4. The register burst access control method of claim 3, wherein step M1 comprises:
respectively writing the state signals related to the write request, the data signals related to the write request and the state signals related to the read request which are received through different channels into different FIFOs; the write request related status signals include: write address, write data length, write data width; the write request related data signals include: writing data, a valid writing section mark and a valid mark of the last data of the current writing data; the read request related status signals include: reading address, reading data length and reading data width;
when the FIFOs corresponding to the status signals relevant to the write request and the data signals relevant to the write request have data, extracting the write request from the corresponding FIFOs and generating arbitration status marks for the write request; when the FIFO corresponding to the status signal related to the read request has data, extracting the read request from the corresponding FIFO and generating an arbitration status flag for the read request;
step M2 includes: and arbitrating the read request and the write request according to arbitration status flags carried by the read request and the write request so as to convert the time sequence of only one of the read request and the write request through the interface protocol at the same time.
5. The register burst access control method of claim 1, wherein the transmit interface protocol timing comprises:
a reqValid signal, which is used to mark whether the current request is valid or not when a read request or a write request is received;
a reqRead signal for marking whether a read operation or a write operation is currently selected when a read request or a write request is received;
the reqCmd signal identifies the type of the transferred data at a first moment on the premise that the reqValid signal is valid, and each moment represents whether the current access is valid or whether the current access is the last data to be transferred from a second moment;
the data processing device comprises a reqAddrData signal and a data processing unit, wherein the reqAddrData signal transmits an initial address of a slave device which needs to be accessed by a read request or a write request at a first moment on the premise that a reqValid signal is effective; if the transmitted write requests are from the second moment, sequentially transmitting the write data at each moment; if a read request is passed, any data may be transferred.
6. The register burst access control method of claim 5, wherein the transmit interface protocol timing further comprises: a reqUserInfo signal, which is used for function extension.
7. The register burst access control method of claim 1, wherein receiving an interface protocol timing comprises:
an ackValid signal for indicating whether the currently fed back response data is valid;
an ackError signal for identifying whether an error is contained in the reply data;
ackData signals, which are used to convey specific response data or to transmit error codes in the event of an error in the response data.
8. The register burst access control method of claim 7, wherein receiving an interface protocol timing sequence further comprises:
an ackUserInfo signal, which is used for functional extension.
9. The register burst access control method of claim 1, further comprising: connecting the interfaces of each sub-module of the slave equipment in a cascade mode;
when the slave device receives a request command through the same data transmission channel, wherein the request command is the read request or the write request, each submodule in the slave device is sequentially prompted to be matched and confirmed with an access address in the request command according to the cascade order,
if the addresses are the same, performing request command response in the current sub-module to generate response data; after the response data is formed, the request command and the response data are synchronously sent to the next submodule;
if the addresses are different, directly sending the data received by the current sub-module to the next sub-module;
and if the current submodule is the last submodule, only the response data is fed back through the same data channel.
10. The register burst access control method of claim 1, further comprising: making star connection for the interface of each sub-module of the slave device;
adding a sequence identifier to each request command, wherein the request command is the read request or the write request;
when the slave equipment receives a request command through the same data transmission channel, searching a sub-module matched with the address according to the access address of the request command;
request command response is carried out in the address matching sub-module to generate response data, and meanwhile, the same sequence identification as the request command is added to each response data;
and outputting each response data in sequence in the same data channel according to the generation sequence of the sequence identifier in the request command.
11. An electronic device comprising a memory and a processor, said memory storing a computer program operable on said processor, wherein said processor implements the steps in the register burst access control method of any of claims 1-10 when executing said program.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the register burst access control method according to any one of claims 1 to 10.
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Shengke Communication Co.,Ltd. Address before: Xinghan Street Industrial Park of Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Applicant before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
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