JPH03256150A - Command response control system for bus multiplexed system - Google Patents

Abstract

PURPOSE:To remove processing for checking the response of a port state by hard access by preparing a status table for holding the status of a port or e like, referring the contents of the table and determining a port for responding the command. CONSTITUTION:When a hard error interruption is inputted, an interruption handler (control part 22) executes hard error interruption processing. The control part 22 analyzes the contents of the error, decides the sort of the error and hard-accesses a port through an internal bus 25 to close a port (e.g. port 20) of the error generation side or turn a bus (e.g. 3a) to a disable state. Then the control part 22 changes the value of a status table 23a in a memory 23. Open and enable states (e.g. flag '1') are respectively set up in the table 23a as initial values. In the case of the hard error of the port 20 e.g., the opened state of the port 20 is rewritten to its closed state. In the case of the hard error of the bus 3a, the enable state of the bus 3a in the table 23a is rewritten to its disabled state.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 4) Means for solving the problem to be solved by the invention (Figure 1) Working example (a) 1 Description of Embodiments (Figures 2 and 3) (bl Description of Other Embodiments Effects of the Invention [Summary] In a bus multiplexing system in which a pair of devices are connected via a plurality of buses, a command from one device Regarding the command response control method in which another device accepts, executes, and responds with the execution result, the purpose of this method is to prevent a delay in response to a command. In a bus multiplexing system in which the other device receives a command sent via a bus, executes the command, and responds with the execution result via the bus, the other device sends a command to each of the plurality of lotuses. A plurality of ports are provided correspondingly to control communication via the bus, a state table having status information for each port indicating whether or not communication is possible from the port via the bus, and upon response of execution results, and a control section that refers to the state table, and the control section accesses a communicable port according to the result of referring to the state table and responds with an execution result.

[Industrial application field]

The present invention relates to a command response control method in a bus multiplexing system in which a pair of devices are connected by a plurality of buses, in which another device receives a command from one device, executes it, and responds with the execution result.

With the spread of computer systems, its importance is increasing.

For this reason, especially in financial institutions, etc., one part of the system is
There is a need for a non-stop computer that will not shut down even if a failure occurs in the section.

Nonstop computers generally have dual main parts, so that even if one goes down due to a failure, the other computer continues to operate, and the buses that connect the devices are also redundant.

In this bus duplication, if the bus that accepted the command becomes impaired, it is necessary to use the other bus to return a response, and control for this is required.

[Conventional technology]

FIG. 4 is an explanatory diagram of the prior art.

As shown in FIG. 4(A), a host computer 1 and an adapter 2 are connected by two buses 3a and 3b, and input/output devices such as a terminal 4a and a file device W4b are connected to the adapter 2.

In this system, I10 from host computer 1
The adapter 2 controls the input/output devices 4a and 4b according to commands and executes the commands, but since two busses 3a and 3b are provided, during normal operation, communication is performed using the two buses 3a and 3b. When one bus 3a fails, the other bus 3b is used to communicate, ensuring non-stop communication.

This adapter 2 includes ports 20, which are provided corresponding to the buses 3a and 3b, and which control communication by the buses 3a and 3b.
21 is provided, and ports 20.21 issue an interrupt to an interrupt handler controlled by operational firmware operating under the MPU, and an instruction is executed.

The instruction execution sequence in such a system is as shown in FIG. This is notified to the interrupt handler (interrupt handler), and the control unit 22 reads and executes the I10 instruction.

For example, a read command causes a specified input/output device to perform a read operation, and a write command causes a specified input/output device to perform a write operation.

After executing this command, the control unit 22 returns the execution result to the host 1 as a response. For example, a read command is read data, and a write command is a write result.

Generally, a response is sent via the bus from the port that received the command, but there is a time period between receiving the command and returning the response, during which time other commands are received or other responses are made.

Therefore, a failure may occur in the port that accepted the command or the bus connected thereto.

Therefore, before returning a response, the control unit 22 accesses the port that accepted the response, captures the status, determines whether a failure (error) has occurred in that port or bus, and if no failure has occurred, the controller 22 Re-access the accepted port,
The response was placed on the bus, and if a failure occurred, the port on the opposite side was accessed and the response was returned from there.

[Problem to be solved by the invention]

However, in the conventional technology, when returning a response to a command, the reception always hard-accesses the port and confirms its status, resulting in a delay in the response to the command and a decrease in execution response. There was a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a command response control method for a bus multiplexing system that can prevent delays in responses to commands.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, in the present invention, a pair of devices 1.2 are connected by a plurality of buses 3a and 3b, and a command sent from one device 1 through the buses is sent to the other device 2. In a bus multiplexing system that accepts commands, executes commands, and responds with execution results via the bus, the other device 2 is provided corresponding to each of the plurality of buses 3a and 3b, and the other device 2 is provided corresponding to each of the plurality of buses 3a and 3b, A plurality of ports 20.21 that control communication, a state table 23a that has state information for each port 20.21 as to whether or not communication is possible from the port via the lotus, and 23a, and the control unit 22 accesses a communicable port according to the reference result of the status table 23a and responds with the execution result. It is.

[Effect]

In the present invention, a state table 23a is provided that has state information on communication availability for each port 20 and 21, and when the control unit 22 (interrupt handler) responds with an execution result, it refers to the state table 23a and Since the control unit 22 determines the port that responds to the command, the control unit 22 can omit the sequence of hard accessing each port and checking the status when responding, preventing delays in command response, and increasing the speed of command response by modifying the hardware. Can be executed without

〔Example〕

fal - Description of Examples FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figures, the same parts as those shown in FIGS. 1 and 4 are indicated by the same symbols.

Ports 20.21 are bus drivers and bus receivers.
, lotus control units 20a and 21a including path controllers, and error detection units 20b and 21 that detect errors in these units.
b, and status registers 2Qc and 21c that hold the hardware status of the bus control unit 20a121a.

The control unit 22 (interrupt handler) is controlled by operational firmware running under a microprocessor (MPU), and performs command analysis, execution control, response control, and the like.

A memory 23 is provided with the aforementioned status table 23a, and a reception table 23b for storing commands and ports for reception, and is also used as a work memory of the MPU 22 and the like.

The status table 23a shows the oven (
open: operating)/close (close: not operating)
Status column and bus 3a, 3b enable (Enable)
: Operational)/Disabled (Disable: Operational not possible) status column is for each port 20.21 (Bus 3a, 3b)
provided for each.

24 is an I10 controller, and input/output devices 4a, 4
25 is an internal bus that controls MPU 22
It connects the ports 20, 21, memory 23, and I10 controller 24.

FIG. 3 is a processing flow diagram of one embodiment of the present invention, and FIG. 3(A) is a hard error interrupt processing flow diagram;
Figure (B) is a normal interrupt processing flow diagram.

First, FIG. 3(A) will be explained.

The error detection units 20b and 21b of the ports 20 and 21 detect whether an error has occurred in the bus control units 20a and 21a and the bus 3a13b.

When the error detection units 20b and 21b detect a hard error, they issue a hard error interrupt to the interrupt handler.

The interrupt handler executes hard error interrupt processing when a hard error interrupt occurs.

The interrupt handler analyzes the contents of the error, determines the type of error (port or bus), and closes the port where the error occurred (for example, port 20) or disconnects the bus (for example, bus 3a). In order to enable the port, the port is hard accessed via the internal bus 25.

That is, if an error occurs from the bus control section 20a, a port close or bus disable flag is written in the control register of the bus control section 20a.

Next, the interrupt handler executes the state table 23 in the memory 23.
Change the value of a.

The state table 23a has an open state and an enabled state (for example, flag 1'') set as initial values.

For example, if there is a hard error in the port 20, the open state (flag l") of the port 20 is rewritten to the closed state (flag "O").

Also, if there is a hard error on the bus 3a, the status table 23a
The enable state (flag "1") of the bus 3a is rewritten to the disable state (flag "o").

Then, the interrupt processing ends.

Next, the normal interrupt processing shown in FIG. 3(B) will be explained.

(2) The host 1 issues an I10 command to the adapter 2 via the bus 3a or 3b.

This I10 instruction is accepted by port 20 or 21, and the accepting port issues an interrupt to the interrupt handler.

1 2 ■ The interrupt handler reads the I10 instruction from the accepted port via the internal bus 25, stores it in the acceptance table 23b, and then analyzes the type of instruction.

■ If the instruction is a read/write instruction, the interrupt handler executes the read/write instruction.

For example, in the case of a read command to the file device 4b, the interrupt handler is sent to the I10 controller 2 via the internal bus 25.
4 to cause the file device 4b to perform a read operation.

■ In executing this instruction and responding with the execution result, the interrupt handler uses the state table 23a in the memory 23.
See.

In other words, the reception of the command to respond uses the port in the table 23.
b, and refer to the status column of the relevant port and bus in the status table 23a.

■ If this status field indicates bus enable and the port is open, the interrupt handler
It hard accesses the port (for example, baud 20) that accepted the data via the port 20, sends the execution result, and responds with the execution result from the port 20 to the bus 3a.

Conversely, when the interrupt handler's status column is enabled and the port is not open, the reception assumes that a port or bus error has occurred, hard accesses the opposite port (for example, port 21), and displays the execution result. is sent, and the execution result is responded from the port 21 to the bus 3b.

(2) On the other hand, as a result of the analysis of the instruction in step (2), if the instruction is a configuration control instruction, the state of the port/bus is changed according to the instruction.

That is, the configuration control command is a command for the host 1 to enable or open an error bus or port when the bus or port is restored by repair or the like.

Therefore, the interrupt handler hard accesses the port according to the instruction and changes the state of the control register to enable and open.

At the same time, the status column of the port and bus in question in the status table 23a of the memory 23 is changed to open or enabled, and the process ends.

3 4 In this way, the memory 23 is provided with the table 23a that holds the state of the port or bus, and by referring to the table 23a when responding with the execution result of a command, the responding port is determined and the port is selected. Hard access and respond.

Therefore, when responding, there is no need to hard access the port to grasp the status, and only refer to the table, so command responses can be executed without delay. This can be achieved without modification.

(bl Description of Other Embodiments In the above embodiment, an example of communication between the host and the adapter was explained, but other types may be used, and the number of buses is not limited to two, but may be three or more. .

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, a state table is provided that holds the states of ports, etc., and the port that responds to a command is determined by referring to the state table. When responding, the process of confirming each response by accessing the hardware is removed, which has the effect of speeding up the command response, and also has the advantage of being able to achieve this without modifying the hardware.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a processing flow diagram of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of a prior art. In the figure, 1-host, 2-adapter, 3a, 3b-bus, 5 6 20.21-port, 22-control unit, 23a-state table.

Claims (1)

[Claims] A pair of devices (1, 2) are connected by a plurality of buses (3a, 3b), and a command sent via the bus of one device (1) is transmitted to the other device (2). ) accepts commands, executes commands, and responds with execution results via the bus, in which the other device (2) is provided corresponding to each of the plurality of buses (3a, 3b). a plurality of ports (20,
21), and a status table (23) that has status information for each port (20, 21) indicating whether or not communication is possible from the port via the bus.
a); and a control unit (22) (interrupt handler) that refers to the status table (23a) when responding with an execution result, and the control unit (22) refers to the status table (23a). A command response control method for a bus multiplexing system characterized by accessing a communicable port according to the result and responding with the execution result.