JP2012163995A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a function by a PCI Express card.SOLUTION: An information processing device comprises: a microprocessor 120; a PCI Express switch 140; and an IO controller 110. The IO controller 110 comprises: a first PCI Express port 111; a first PCI Express interface part; a second PCI Express port 112 connected to a downstream port of a PCI Express switch 140; a second PCI Express interface part which is connected to the second PCI Express port 112 and converts a PCI Express packet and an internal signal of the IO controller 110; a first PCI Express interface part; and a memory access mechanism connected with the second PCI Express interface part by an internal bus respectively.

Description

  The present invention relates to an information processing apparatus. In particular, the present invention relates to an information processing apparatus whose function is expanded by a peripheral component interconnect bus (PCI) Express card.

  FIG. 12 shows an example of a use environment of a known information processing apparatus 900. The known information processing apparatus 900 includes a microprocessor 920, a memory 930, a PCI Express switch 940, and a plurality of PCI Express cards 950a to 950d (hereinafter collectively referred to as PCI Express cards 950).

  The microprocessor 920 has a built-in root complex. The microprocessor 920 is electrically connected to the memory 930 through the bus 961. In addition, the root port 921 of the microprocessor 920 is electrically connected to the upstream port 942 of the PCI Express switch 940 via the PCI Express link 973.

  On the other hand, the downstream port 943 of the PCI Express switch 940 is electrically connected to the port 951a of the PCI Express card 950a via the PCI Express link 974. Similarly, the downstream ports 944 to 946 of the PCI Express switch 940 are electrically connected to the PCI Express card 950 via the PCI Express link. Further, the PCI Express card 950 is electrically connected to the peripheral device 700 through a path.

  The known information processing apparatus 900 is as follows when the software operating on the microprocessor 920 accesses the PCI Express card 950 in order to control data transfer between the information processing apparatus 900 and the peripheral device 700. Operate.

  First, the software executes an instruction for accessing the memory mapped I / O space corresponding to the target PCI Express card 950 to the microprocessor 920. This instruction is the same as that for accessing the memory 930, and is generally a load instruction and a store instruction. Accordingly, the microprocessor 920 transmits a signal for accessing the memory mapped I / O space designated by the software to the built-in root complex, and the root complex transmits the corresponding packet from the root port 921. The PCI Express card 950 that has received the packet performs processing corresponding to the packet, and if it is a memory read request, returns a completion together with the read data to the microprocessor 920 as a requester. In the case of a memory write request, it is posted. The root complex that has received the completion from the PCI Express card 950 passes the received data to the microprocessor 920, and the instruction executed by the software is completed.

  Here, consider a case where the PCI Express card 950 cannot normally respond to a memory read request from the microprocessor 920 due to a failure. If the PCI Express card 950 does not respond to a memory Read request, or if completion returns a complete abort or an unsupported request, the root complex can pass the read data to the microprocessor 920. Disappear. Therefore, the microprocessor 920 cannot complete the instruction and enters a stalled state. In addition, when the root complex detects a timeout due to no response from the completer, or returns a completion abort or an unsupported request, the root complex may report the occurrence of a fatal failure to the microprocessor 920. In 920, the entire information processing apparatus 900 is reset to attempt recovery.

  As described above, in the known information processing apparatus 900, when the access of the memory mapped I / O space from the microprocessor 920 is not normally completed due to the failure of the PCI Express card 950, even if the failure of the single PCI Express card 950 occurs. However, there is a problem that it becomes an obstacle to the information processing apparatus 900 as a whole.

  By the way, as a bus failure processing method, a technique for controlling a PCI bus in a computer system is known (for example, see Patent Document 1).

  As a system monitoring program, a technique is known in which a system can be stably operated without being affected by an input / output bus failure (see, for example, Patent Document 2).

JP 2005-215809 A

  The technique described in Patent Document 1 is a technique related to the PCI standard. However, the PCI standard has no concept of timeout for request reply. Therefore, depending on the technique described in Patent Document 1, it is not possible to cope with a case where there is no response from the PCI device.

  In order to solve the above-described problem, according to a first aspect of the present invention, there is provided an information processing apparatus whose function is expanded by a PCI Express card, wherein a microprocessor, a PCI Express card, and a microprocessor are respectively connected by a PCI Express link. A PCI Express switch to be connected, a microprocessor, and an IO controller connected to the PCI Express switch by a PCI Express link, respectively, to access the memory mapped I / O space of the PCI Express card. A first PCI Express port connected to the processor root port and a first PCI Express port connected to the first PCI Express port. A PCI Express interface unit for converting internal signals of the host and the IO controller, a second PCI Express port connected to the downstream port of the PCI Express switch, and a PCI Express port connected to the second PCI Express port. A second PCI Express interface unit for converting an Express packet and an internal signal of the IO controller, a first PCI Express interface unit, and a memory access mechanism connected to the second PCI Express interface unit by an internal bus. .

  In addition, as described above, the summary of the invention does not enumerate all necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  As is apparent from the above description, in the present invention, when the software operating in the microprocessor accesses the memory mapped I / O space of the PCI Express card, the memory access mechanism of the IO controller is used.

  In this way, depending on the present invention, even if a failure occurs in the PCI Express card and the completion times out or the microprocessor abort or other microprocessor is unexpected, the IO controller memory access mechanism Will not propagate as a catastrophic failure to the microprocessor.

  Therefore, according to the present invention, recovery processing can be performed by software, and it is possible to prevent a failure from spreading to the entire information processing apparatus due to a failure of the PCI Express card.

It is a figure which shows an example of the information processing apparatus 100 utilization environment which concerns on one Embodiment. 2 is a diagram illustrating an example of a block configuration of an IO controller 110. FIG. 3 is a diagram illustrating an example of mapping of a memory mapped I / O space in the information processing apparatus 100. FIG. 4 is a diagram illustrating an example of mapping of a memory mapped I / O space 370 of the IO controller 110. FIG. 3 is a diagram illustrating an example of a request control register 210. FIG. 5 is a diagram illustrating an example of a request address register 220. FIG. 5 is a diagram illustrating an example of a reply status register 230. FIG. 4 is a diagram illustrating an example of a data register 240. FIG. FIG. 3 is a diagram illustrating an example of a timeout register 250. 3 is a diagram illustrating an example of an operation flow of the information processing apparatus 100. FIG. 6 is a diagram illustrating another example of an operation flow of the information processing apparatus 100. FIG. FIG. 3 is a diagram illustrating an example of a usage environment of a known information processing apparatus 900.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and are combinations of features described in the embodiments. Not all are essential to the solution of the invention.

  FIG. 1 shows an example of an environment for using an information processing apparatus 100 according to an embodiment. The information processing apparatus 100 is an apparatus that expands functions by using a PCI Express card.

  The information processing apparatus 100 includes an IO (input-output) controller 110, a microprocessor 120, a memory 130, a PCI Express switch 140, and a plurality of PCI Express cards 150a to 150d (hereinafter collectively referred to as PCI Express cards 150). . The microprocessor 120 has a PCI Express root complex.

  The IO controller 110 has two PCI Express ports 111 and 112. The microprocessor 120 has two root ports 121 and 122. The PCI Express switch 140 has one upstream port 141 and five downstream ports 142-146. The PCI Express card 150a has a port 151a.

  In addition, the PCI Express cards 150b to 150d other than the PCI Express card 150a have the same components as the components of the PCI Express card 150a. In the following description, when distinguishing which component of the PCI Express card 150 is a component of the PCI Express card 150, the same subscript (a to d) as the PCI Express card 150 having each component. ) At the end of each component. For example, the port 151a, the port 151b, and the port 151c indicate the components of the PCI Express card 150a, the PCI Express card 150b, and the PCI Express card 150c, respectively.

  Further, in the following description, the function and operation of a component that is not given a subscript indicates the function and operation of any component that is assigned the same reference numeral. For example, the functions and operations described for the port 151 indicate the functions and operations of the ports 151a to 151d.

  The PCI Express port 111 of the IO controller 110 is electrically connected to the root port 122 of the microprocessor 120 via the PCI Express link 171. In addition, the PCI Express port 112 of the IO controller 110 is electrically connected to the downstream port 142 of the PCI Express switch 140 via the PCI Express link 173.

  On the other hand, the microprocessor 120 is electrically connected to the memory 130 via the bus 161. In addition, the root port 121 of the microprocessor 120 is electrically connected to the upstream port 141 of the PCI Express switch 140 via the PCI Express link 172.

  On the other hand, the downstream port 143 of the PCI Express switch 140 is electrically connected to the port 151a of the PCI Express card 150a via the PCI Express link 174. Similarly, the downstream port 144 of the PCI Express switch 140 is electrically connected to the port 151b of the PCI Express card 150b via the PCI Express link 175. Similarly, the downstream port 145 of the PCI Express switch 140 is electrically connected to the port 151c of the PCI Express card 150c via the PCI Express link 176. Similarly, the downstream port 146 of the PCI Express switch 140 is electrically connected to the port 151d of the PCI Express card 150d via the PCI Express link 177.

  On the other hand, the PCI Express card 150a is electrically connected to the peripheral device 700a via a path 801. Similarly, the PCI Express card 150b is electrically connected to the peripheral device 700b via a path 802. Similarly, the PCI Express card 150c is electrically connected to the peripheral device 700c via a path 803. Similarly, the PCI Express card 150d is electrically connected to the peripheral device 700d via a path 804.

  FIG. 2 shows an example of a block configuration of the IO controller 110. The IO controller 110 has two PCI Express ports 111 and 112, which are connected to the PCI Express interface units 113 and 114 that convert the internal signal of the IO controller 110 and the PCI Express interface, respectively. The PCI Express interface units 113 and 114 analyze packets received from the PCI Express ports 111 and 112, convert them into internal signals, output them to the IO controller, and convert internal signals from the IO controller into corresponding packets. And is responsible for processing to transmit to the PCI Express port.

  The IO controller 110 has a memory access mechanism 200 for requesting PCI Express memory access to the PCI Express interface unit 114 and the PCI Express port 112, and the PCI Express interface units 113 and 114 and internal buses 115 and 116. Connected through. This memory access mechanism 200 has five control registers 210 to 250 for issuing a memory request to PCI Express and reading / writing the memory mapped I / O space. It is mapped to space. These control registers 210 to 250 can be accessed by accessing the corresponding memory mapped I / O space by the software on the microprocessor 120 through the PCI Express port 111 and the PCI Express interface unit 113. The software can issue a memory request to PCI Express using the memory access mechanism 200. In addition, the internal structure of the memory access mechanism 200 is the same as that in a normal PCI Express, and the description thereof is omitted. Details of each register will be described in the section related to the memory mapped I / O space.

  FIG. 3 shows an example of mapping of the memory mapped I / O space in the information processing apparatus 100. The memory mapped I / O space is mapped as shown in FIG. 3, and the microprocessor 120, the IO controller 110, and the PCI Express cards 150a to 150d issue memory requests to the addresses of the target components. Data can be read and written.

  FIG. 4 shows an example of mapping of the memory mapped I / O space 370 of the IO controller 110. The memory mapped I / O space of the IO controller 110 is as shown in FIG. 4, and the registers 210 to 250 of the memory access mechanism 200 are mapped to the memory mapped I / O space, respectively.

  FIG. 5 shows an example of the request control register 210. The request control register 210 controls the issuance of a memory request. The read bit 211 for instructing the memory read in the memory mapped I / O space, the write bit 212 for instructing the memory write, and the size of the read / write are designated. The corresponding instruction is notified to the PCI Express interface unit 114 when each bit is 1, and the corresponding request is transmitted as a packet from the PCI Express port 112.

  FIG. 6 shows an example of the request address register 220. The request address register 220 is a register for designating a memory mapped I / O space address for performing the memory read and the memory write, and needs to be set before the memory request is issued by the request control register 210.

  FIG. 7 shows an example of the reply status register 230. The reply status register 230 is a register for confirming a reply state from the completer, a timeout or the like when the memory is read. The END bit 231 indicating that the completion has been received, and TO indicating that the completion timeout has occurred. Bit 232, SC bit 233 indicating that the received completion is completed normally, UR bit 234 indicating an unsupported request, CRS bit 235 indicating that a configuration retry is being performed, CA bit 236 indicating a completer abort, and received data Has an ERR bit 237 indicating that it is illegal. The reply status register 230 is set according to the completion received from the PCI Express port 112 by the PCI Express interface unit 114. The software needs to monitor the reply status register 230 to confirm the reply status.

  FIG. 8 shows an example of the data register 240. The data register 240 sets data to be written in the case of the memory write. In the case of the memory read, the data register 240 stores a value read when the reply status register 230 has the END bit 231 and the SC bit 233 set to 1. In the case of the memory write, the software needs to write a value to the request control register 210 and set a value to be written to the data register 240 before issuing the memory write request. In the case of the memory Read, the software needs to read the reply status register 230 and check the END bit 231 and the SC bit 233, and then read the data register 240. In the case of the memory write, the data register 240 is read by the PCI Express interface unit 114 after a value is set in the request control register 210, and a corresponding packet is generated. When the completion that completes normally is received, the data read from the packet is set by the PCI Express interface unit 114.

  FIG. 9 shows an example of the timeout register 250. The time-out register 250 sets a time-out time for completion from the completer in microseconds when the memory is read. The memory access mechanism 200 passes a time-out time from when a memory read request is issued to the PCI Express interface unit 114 to when a completion is received by the time-out register 250, and the PCI Express interface unit 114 stores the memory in the PCI Express port 112. If the completion cannot be received within the time specified by the timeout register 250 after issuing the Read request, the TO bit 232 of the reply status register 230 is set to 1.

  FIG. 10 shows an example of the operation flow of the information processing apparatus 100. In the information processing apparatus 100, since software operating on the microprocessor 120 controls data transfer between the information processing apparatus 100 and the peripheral device 700, the memory mapped I / O space 220 ~ of the PCI Express cards 150a to 150d is used. In the case of accessing 250, in the case of the memory write, the operation flow is as shown in FIG.

  In the case of the memory write to the memory mapped I / O space 220 to 250 of the PCI Express card 150a to 150d, the software accesses the memory mapped I / O space 270 of the IO controller 110 to access each register 210 of the memory access mechanism 200. ~ 250 are set, and a memory write request is issued to the PCI Express card 150a-d. The software sets a write destination memory mapped I / O space address in the request address register 220 (S101), and sets a value to be written in the data register 240 (S102). Then, the write bit 212 is set to 1 in the request control register 210, and a value for setting the size to be written in the size 213 is written (S103). As a result, the memory access mechanism 200 issues a memory write request issuance request to the PCI Express interface unit 114 based on the values of the registers 210 to 250, and the PCI Express interface unit 114 generates a corresponding packet to generate the PCI Express. Send to port 112. The packet is routed as a completer to the PCI Express cards 150a to 150d, and data is written into the designated memory mapped I / O space by the completer. Since the memory write in PCI Express is posted, the memory write process ends here.

  FIG. 11 shows another example of the operation flow of the information processing apparatus 100. In the information processing apparatus 100, since software operating on the microprocessor 120 controls data transfer between the information processing apparatus 100 and the peripheral device 700, the memory mapped I / O space 220 ~ of the PCI Express cards 150a to 150d is used. In the case of accessing 250, the operation flow as shown in FIG.

  Next, when data is read from the memory mapped I / O spaces 220 to 250 of the PCI Express cards 150a to 150d, the software accesses the memory mapped I / O space 270 of the IO controller 110 to access each memory access mechanism 200. The registers 210 to 250 are set, and a memory read request is issued to the PCI Express cards 150a to 150d. The software sets the memory mapped I / O space address of the read destination in the request address register 220 (S201), and sets the completion timeout time in microseconds in the timeout register 250 (S202). Then, the Read bit 211 is set to 1 in the request control register 210, and a value for setting the size to be read is written in the Size 213 (S203). As a result, the memory access mechanism 200 issues a memory read request issuance request to the PCI Express interface unit 114 based on the values of the registers 210 to 250, and the PCI Express interface unit 114 generates a corresponding packet to generate the PCI Express. Send to port 112. Then, the packet is routed to the completer, and the completer reads data from the memory mapped I / O space according to the contents of the packet, generates a completion packet for the requester, and transmits it to the requester.

  The completion packet transmitted from the completer is routed to the IO controller 110 which is a requester, and the PCI Express interface unit 114 receives and analyzes it, and according to the completion status of the packet, SC bit 233 in the reply status register 230, The UR bit 234, CRS bit 235, CA bit 236 and ERR bit 237 are set to 1, and the END bit 231 is set to 1.

  After writing a value in the request control register 210 and issuing a memory read request, the software reads the reply status register 230 and waits until the END bit 231 or the TO bit 232 becomes 1 (S204, S205, S206). When the END bit 231 becomes 1, the SC bit 233 is checked to check whether the completion is completed normally (S207). If the SC bit 233 is 1, the memory register I / O is read from the data register 240. The data read from the O space is read and the process is normally terminated (S208). When the SC bit 233 is 0, the completer has aborted, the request has not been supported, the configuration has been performed, or the data of the completion packet has been corrupted, so the process ends as an abnormal end. At this time, the software performs completer recovery processing. Since the contents of the recovery process are outside the scope of the present invention, the description thereof is omitted.

  Next, consider a case where the completion for the memory read request is not returned due to a failure of the PCI Express card 150a-d. The operation is the same until the memory read request is issued. After the PCI Express interface unit 114 issues a memory read request, it waits for completion from the completer for the time specified by the timeout register 250. However, because completion is not returned from the completer, a timeout occurs, and PCI Express The interface unit 114 sets the TO bit 232 of the reply status register 230 of the memory access mechanism 200. The software reads the reply status register 230 and waits for the END bit 231 and the TO bit 232 to become 1 (S205, S206). In this case, since the TO bit 232 is set to 1, the software determines a completion time-out and terminates the processing as an abnormal end.

  As described above, in the information processing apparatus 100 of FIG. 1, when software operating on the microprocessor 120 accesses the memory mapped I / O spaces 220 to 250 of the PCI Express cards 150a to 150d, the memory access of the IO controller 110 is performed. By using the mechanism 200, even if the completion times out due to a failure of the PCI Express card 150a-d or the microprocessor such as a complete abort is unexpected, the memory access mechanism 200 of the IO controller 110 can Therefore, it is not propagated to the microprocessor 120 as a fatal failure, but can be recovered by software, and information processing is performed by the failure of the PCI Express cards 150a to 150d. The entire device 100 failure can be prevented from being spread.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

100 Information processing device 110 IO controller 111 PCI Express port 112 PCI Express port 113 PCI Express interface unit 114 PCI Express interface unit 114 PCI Express interface unit 115 Internal bus 116 Internal bus 120 Microprocessor 121 Root port 122 Root port 130 Memory 140 PCI Express switch 141 Upstream port 142 downstream port 143 downstream port 144 downstream port 145 downstream port 146 downstream port 150 PCI Express card 151 port 161 bus 171 PCI Express link 172 PCI Express link 173 PCI Express link 174 PCI Express link 175 PCI Express link 176 PCI Express link 177 PCI Express link 200 PCI Express link 200 Memory access mechanism 210 Request control register 211 Read bit 212 Write bit 213 Size bit 220 Request address register 230 Reply status register 231 D 232 TO bit 233 SC bit 234 UR bit 235 CRS bit 236 CA bit 237 ERR bit 240 Data register 250 Timeout register 310 Memory mapped I / O space 320 of memory 130 Memory mapped I / O space of PCI Express card 150d 330 PCI Express card 150c Memory-mapped I / O space 340 Memory-mapped I / O space 350 of the PCI Express card 150b Memory-mapped I / O space 360 of the PCI Express card 150a Memory-mapped I / O space 370 of the PCI Express switch 140 Memory of the IO controller 110 Mapped I / O space 371 Memory mapped I / O space 372 in request control register 210 Memory mapped I / O space 373 in request address register 220 Memory mapped I / O in reply status register 230 Space 374 Memory mapped I / O space 375 of data register 240 Memory mapped I / O space 700 of timeout register 250 Peripheral device 801 Path 802 Path 803 Path 804 Path

Claims (7)

An information processing apparatus whose function is expanded by a PCI Express card,
A microprocessor;
A PCI Express switch connected to the PCI Express card and the microprocessor, respectively, by a PCI Express link;
An IO controller connected to the microprocessor and the PCI Express switch by a PCI Express link, respectively, and accessing a memory mapped I / O space of the PCI Express card;
The IO controller
A first PCI Express port connected to a root port of the microprocessor;
A first PCI Express interface unit connected to the first PCI Express port for converting a PCI Express packet and an internal signal of the IO controller;
A second PCI Express port connected to the downstream port of the PCI Express switch;
A second PCI Express interface unit connected to the second PCI Express port for converting a PCI Express packet and an internal signal of the IO controller;
An information processing apparatus comprising: a memory access mechanism connected to the first PCI Express interface unit and the second PCI Express interface unit by an internal bus. The information processing apparatus according to claim 1, wherein the memory access mechanism issues a memory request for a memory mapped I / O space to the second PCIe interface unit. The information processing apparatus according to claim 2, wherein the memory access mechanism includes a register for managing a completion state of the issued memory request. The information processing apparatus according to claim 3, wherein the register is mapped in a memory mapped I / O space. The information processing apparatus according to claim 4, wherein software operating in the microprocessor accesses the register via the first PCI Express port and the first PCI Express interface unit. 6. The information processing according to claim 5, wherein software operating in the microprocessor issues a memory request to a memory mapped I / O space of the PCI Express card by accessing a register of a memory access mechanism of the IO controller. apparatus. 7. The software operating in the microprocessor reads the data read from the memory mapped I / O space from the register when the completion of the memory read request is completed after checking the completion state. Information processing device.

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