JPS5478644A - Interruption control system - Google Patents
Interruption control systemInfo
- Publication number
- JPS5478644A JPS5478644A JP14625577A JP14625577A JPS5478644A JP S5478644 A JPS5478644 A JP S5478644A JP 14625577 A JP14625577 A JP 14625577A JP 14625577 A JP14625577 A JP 14625577A JP S5478644 A JPS5478644 A JP S5478644A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- interruption
- adaptors
- input
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
Abstract
PURPOSE: To ensure the interruption without lowering the working efficiency of more than one of the operation system by forming the control system so that only the processor that is under execution of the process to receive the input/output device interruption may cause the interruption.
CONSTITUTION: Input/output devices 31W3m share processor 41W4n via common I/O bus 101. In such composite processor system, input/output device adaptors 21W2m plus processor adaptors 11W1n are provided between bus 101, devices 31W 3m and processors 41W4n. Then the processor name register is provided to adaptors 21W2m to show which processor the devices 31W3m are used to, and the ten process name register is provided to adaptors 11W1n to show the process name which is under execution. When a coincidence is obtained between the address of the input/ output order and that of devices 31W3m, the using processor name is set to the processor name register. Thus, the interruption is controlled via controller 5 for processors 41W4n.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14625577A JPS6041786B2 (en) | 1977-12-05 | 1977-12-05 | interrupt control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14625577A JPS6041786B2 (en) | 1977-12-05 | 1977-12-05 | interrupt control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5478644A true JPS5478644A (en) | 1979-06-22 |
JPS6041786B2 JPS6041786B2 (en) | 1985-09-18 |
Family
ID=15403593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14625577A Expired JPS6041786B2 (en) | 1977-12-05 | 1977-12-05 | interrupt control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041786B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01228054A (en) * | 1988-03-08 | 1989-09-12 | Fujitsu Ltd | Adapter and its control method for multiple cpu system |
JPH01305460A (en) * | 1988-06-03 | 1989-12-08 | Nec Corp | Inter-processor communication system |
-
1977
- 1977-12-05 JP JP14625577A patent/JPS6041786B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01228054A (en) * | 1988-03-08 | 1989-09-12 | Fujitsu Ltd | Adapter and its control method for multiple cpu system |
JPH01305460A (en) * | 1988-06-03 | 1989-12-08 | Nec Corp | Inter-processor communication system |
Also Published As
Publication number | Publication date |
---|---|
JPS6041786B2 (en) | 1985-09-18 |
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