JPS5478644A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS5478644A
JPS5478644A JP14625577A JP14625577A JPS5478644A JP S5478644 A JPS5478644 A JP S5478644A JP 14625577 A JP14625577 A JP 14625577A JP 14625577 A JP14625577 A JP 14625577A JP S5478644 A JPS5478644 A JP S5478644A
Authority
JP
Japan
Prior art keywords
processor
interruption
adaptors
input
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14625577A
Other languages
Japanese (ja)
Other versions
JPS6041786B2 (en
Inventor
Takemi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14625577A priority Critical patent/JPS6041786B2/en
Publication of JPS5478644A publication Critical patent/JPS5478644A/en
Publication of JPS6041786B2 publication Critical patent/JPS6041786B2/en
Expired legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To ensure the interruption without lowering the working efficiency of more than one of the operation system by forming the control system so that only the processor that is under execution of the process to receive the input/output device interruption may cause the interruption.
CONSTITUTION: Input/output devices 31W3m share processor 41W4n via common I/O bus 101. In such composite processor system, input/output device adaptors 21W2m plus processor adaptors 11W1n are provided between bus 101, devices 31W 3m and processors 41W4n. Then the processor name register is provided to adaptors 21W2m to show which processor the devices 31W3m are used to, and the ten process name register is provided to adaptors 11W1n to show the process name which is under execution. When a coincidence is obtained between the address of the input/ output order and that of devices 31W3m, the using processor name is set to the processor name register. Thus, the interruption is controlled via controller 5 for processors 41W4n.
COPYRIGHT: (C)1979,JPO&Japio
JP14625577A 1977-12-05 1977-12-05 interrupt control system Expired JPS6041786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14625577A JPS6041786B2 (en) 1977-12-05 1977-12-05 interrupt control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14625577A JPS6041786B2 (en) 1977-12-05 1977-12-05 interrupt control system

Publications (2)

Publication Number Publication Date
JPS5478644A true JPS5478644A (en) 1979-06-22
JPS6041786B2 JPS6041786B2 (en) 1985-09-18

Family

ID=15403593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14625577A Expired JPS6041786B2 (en) 1977-12-05 1977-12-05 interrupt control system

Country Status (1)

Country Link
JP (1) JPS6041786B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228054A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Adapter and its control method for multiple cpu system
JPH01305460A (en) * 1988-06-03 1989-12-08 Nec Corp Inter-processor communication system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228054A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Adapter and its control method for multiple cpu system
JPH01305460A (en) * 1988-06-03 1989-12-08 Nec Corp Inter-processor communication system

Also Published As

Publication number Publication date
JPS6041786B2 (en) 1985-09-18

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