JPS5543655A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5543655A
JPS5543655A JP11652078A JP11652078A JPS5543655A JP S5543655 A JPS5543655 A JP S5543655A JP 11652078 A JP11652078 A JP 11652078A JP 11652078 A JP11652078 A JP 11652078A JP S5543655 A JPS5543655 A JP S5543655A
Authority
JP
Japan
Prior art keywords
input
output
control unit
channel
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11652078A
Other languages
Japanese (ja)
Inventor
Kazuharu Ishigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11652078A priority Critical patent/JPS5543655A/en
Publication of JPS5543655A publication Critical patent/JPS5543655A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To reduce greatly the load of the software by starting the 2nd input/output channel via the input/output channel control unit while the 1st input/output channel is carrying out the preceding commond and then executing the command via the input/output control unit.
CONSTITUTION: The input/output order given from program 1 is decoded at CPU2 to start channel control unit CH3 by input/output channel control unit CHC9 and via channel 10a. Then CH3 makes the input/output unit carry out the input/output order through input/output control unit IOC-1 if its own device is operative. In case CH3 is executing the preceding command, the busy signal is sent back to CHC9 via bus 10a with no command sent to IOC5-1. Thus CHC9 carries out the command via IOC5-2 for CH4, and as a result the dual channel operation can be given with no intervention of the software. In such way, the load of the software can be reduced greatly.
COPYRIGHT: (C)1980,JPO&Japio
JP11652078A 1978-09-25 1978-09-25 Input/output control system Pending JPS5543655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11652078A JPS5543655A (en) 1978-09-25 1978-09-25 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11652078A JPS5543655A (en) 1978-09-25 1978-09-25 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5543655A true JPS5543655A (en) 1980-03-27

Family

ID=14689163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11652078A Pending JPS5543655A (en) 1978-09-25 1978-09-25 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5543655A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184741A (en) * 1984-09-29 1986-04-30 Hitachi Ltd Interruption control system
JPH05143484A (en) * 1992-05-13 1993-06-11 Hitachi Ltd Interrupt control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184741A (en) * 1984-09-29 1986-04-30 Hitachi Ltd Interruption control system
JPH05143484A (en) * 1992-05-13 1993-06-11 Hitachi Ltd Interrupt control method

Similar Documents

Publication Publication Date Title
JPS5543655A (en) Input/output control system
JPS5730068A (en) Data processing system
JPS54146541A (en) Information process system
JPS5495133A (en) Input/output processing control system
JPS5324743A (en) Bus selector for electronic computer
JPS54137256A (en) Multi-processor equipment
JPS54530A (en) Reference control unit of memory
JPS5559579A (en) Sequence controller
JPS5616361A (en) Facsimile device
JPS5252338A (en) Allotting device of input/output unit machine number
JPS52131436A (en) Interruption control system
JPS55108053A (en) Microprogram high speed control system
JPS55112639A (en) Analog data processing system
JPS5478644A (en) Interruption control system
JPS5490943A (en) Information processing system
JPS55105753A (en) Interruption waiting system
JPS5561837A (en) Channel control system
JPS5379448A (en) Input/output control interface system
JPS545340A (en) Control system for input and output unit
JPS5566015A (en) Shared line state detection system
JPS54534A (en) Advance control system of instruction in information processor
JPS5437645A (en) Computer system
JPS5292448A (en) I/o unit control system
JPS5580140A (en) Inter-channel communication system
JPS5674747A (en) Parallel operation system