JPS55108053A - Microprogram high speed control system - Google Patents

Microprogram high speed control system

Info

Publication number
JPS55108053A
JPS55108053A JP1497579A JP1497579A JPS55108053A JP S55108053 A JPS55108053 A JP S55108053A JP 1497579 A JP1497579 A JP 1497579A JP 1497579 A JP1497579 A JP 1497579A JP S55108053 A JPS55108053 A JP S55108053A
Authority
JP
Japan
Prior art keywords
execution
program
buffer
high speed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1497579A
Other languages
Japanese (ja)
Inventor
Haruki Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1497579A priority Critical patent/JPS55108053A/en
Publication of JPS55108053A publication Critical patent/JPS55108053A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the execution speed of program, by ending the output of high speed buffer and input preparation and performing parallelly the readout of program and execution.
CONSTITUTION: The high speed buffer 2 for auxiliary memory is provided between the microprogram memory 1 and the program execution hardware 3. Further, the program control signal 6 is received with the memory 1, the next instruction is delivered to the program bus line 4 and inputted to the buffer 2. Further, in the hardware 3, when the execution of instruction is finished, the buffer 2 delivers the next instruction to the hardware 3 via the line 5. Further, when the buffer 2 outputs instruction, the memory content is shifted to the output side and the output and input preparations are finished. Thus, the readout and execution of program are made parallelly, the execution speed of pro-ram can be speeded up.
COPYRIGHT: (C)1980,JPO&Japio
JP1497579A 1979-02-14 1979-02-14 Microprogram high speed control system Pending JPS55108053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1497579A JPS55108053A (en) 1979-02-14 1979-02-14 Microprogram high speed control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1497579A JPS55108053A (en) 1979-02-14 1979-02-14 Microprogram high speed control system

Publications (1)

Publication Number Publication Date
JPS55108053A true JPS55108053A (en) 1980-08-19

Family

ID=11875972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1497579A Pending JPS55108053A (en) 1979-02-14 1979-02-14 Microprogram high speed control system

Country Status (1)

Country Link
JP (1) JPS55108053A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166241U (en) * 1981-04-13 1982-10-20
JPS60140432A (en) * 1983-12-28 1985-07-25 Hitachi Ltd Information processing unit
JPS61196332A (en) * 1985-02-27 1986-08-30 Nec Corp Information processing device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166241U (en) * 1981-04-13 1982-10-20
JPS60140432A (en) * 1983-12-28 1985-07-25 Hitachi Ltd Information processing unit
JPH0522934B2 (en) * 1983-12-28 1993-03-31 Hitachi Ltd
JPS61196332A (en) * 1985-02-27 1986-08-30 Nec Corp Information processing device

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