JPS54151333A - Memory system - Google Patents
Memory systemInfo
- Publication number
- JPS54151333A JPS54151333A JP6041278A JP6041278A JPS54151333A JP S54151333 A JPS54151333 A JP S54151333A JP 6041278 A JP6041278 A JP 6041278A JP 6041278 A JP6041278 A JP 6041278A JP S54151333 A JPS54151333 A JP S54151333A
- Authority
- JP
- Japan
- Prior art keywords
- register
- signal
- block
- instruction
- ref
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To enable to effectively process the refresh and the readout/write-in instruction, when they are instructed simultaneously to the memory unit using the memory element requiring refresh. CONSTITUTION:The readout/write-in(R/W) instruction and the refresh(REF) instruction are tentatively held to the registers 34, 35 via the AND circuits 31, 32, and the block coincidence signal representing the concidence of the both instructions, R/W block and REF block is stored in the register 36 via the AND circuit 33. R/W signal is delivered to the memory circuits 20 to 21 for the output of the register 34 and the inversion output of the register 36 via the AND circuit 40. In this case, R/W signal and REF signal are processed so that they can not be duplicated in the same block by controlling the register 34 through the output of the register 36 via the registers 37, 38, 39 and through the AND circuit 42 taking R/W inversion signal as one input.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6041278A JPS54151333A (en) | 1978-05-20 | 1978-05-20 | Memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6041278A JPS54151333A (en) | 1978-05-20 | 1978-05-20 | Memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54151333A true JPS54151333A (en) | 1979-11-28 |
Family
ID=13141431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6041278A Pending JPS54151333A (en) | 1978-05-20 | 1978-05-20 | Memory system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54151333A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60696A (en) * | 1983-06-16 | 1985-01-05 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory |
JPS61122994A (en) * | 1984-11-19 | 1986-06-10 | Fujitsu Ltd | Dynamic type semiconductor storage device |
-
1978
- 1978-05-20 JP JP6041278A patent/JPS54151333A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60696A (en) * | 1983-06-16 | 1985-01-05 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory |
JPS61122994A (en) * | 1984-11-19 | 1986-06-10 | Fujitsu Ltd | Dynamic type semiconductor storage device |
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