JPH0528856B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving Problems Actions Examples Effects of the Invention [Summary] One or more main storage unit (MSU),
1 logically connected to the main storage unit (MSU)
A computer system comprising a main memory control unit (MCU) that controls whether or not one or more access requests can be sent to the main storage unit (MSU) from one or more processing units per unit machine cycle, between the main memory control unit (MCU) and the main memory unit (MSU), an access request bus corresponding to one or more unit data lengths is provided between the main memory control unit (MCU) and the main memory control unit (MSU); ) is transmitted with a data length corresponding to a unit data length or multiple times the unit data length (block access). The unit data (elements) that can be accessed are transmitted sequentially to the main storage unit (MSU).
With the aim of improving the usage efficiency of
The block access to the main memory control unit (MCU) is divided into smaller access units corresponding to the unit data length, and an access request is sent to the main memory unit (MSU) for each unit data length. In the main memory access control method configured to arbitrarily control the transmission order within the block access, the main memory control unit (MCU) is provided with a main memory access control method corresponding to each segment of the main memory unit (MSU). A first priority cycle mechanism is provided that performs a bus conflict check between the access ports that are connected to each other, and a second priority cycle mechanism that performs a bank busy check of unit data in each segment. The cycle mechanism performs a conflict check between the buses provided corresponding to each access port, and the second priority cycle mechanism performs a bank busy check within the bus to determine if the bus is busy. It is configured to issue an access request for each unit of data to each bank.

[Industrial application field]

The present invention has one or more main storage units (MSU), and has one or more processing units logically connected to the main storage units (MSU). A computer system having a main memory control unit (MCU) that controls whether or not one or more access requests can be sent to the main memory unit (MSU), the main memory control unit (MCU) and the main memory unit (MSU) MSU) has one or more access request buses corresponding to each unit data length, and the access request from the processing device to the main memory control unit (MCU) is a unit data length or multiple times the unit data length. The present invention relates to a main memory access control method in a computer system in which data is transmitted (block access) with a data length corresponding to .

In general, in the above-mentioned computer systems, the logic of the priority check mechanism that prioritizes the transmission of access requests to the main storage unit (MSU) is deep, and the logical delay caused by the priority check mechanism increases the logic delay of the computer system. The logic delay of the priority check mechanism needs to be as short as possible because it can lengthen the machine cycle and seriously affect the processing capacity of the computer system.

On the other hand, even if the logic delay in the priority check mechanism is short, multiple cycles (for example, 2
In a mechanism that issues an access request to the main storage unit (MSU) based on the result of a priority check in a cycle, for example, in the case of a block access that transfers multiple units of data (8 bytes) at once. The throughput of data transfer will be significantly reduced.

Therefore, in a computer system that performs block access, a priority check method that can be transmitted every machine cycle is required.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram illustrating a conventional main memory access control system, in which a is a diagram schematically showing a priority check mechanism, and b is a diagram illustrating problems during block access.

In the conventional main memory control unit (MCU) 1, block accesses transmitted to the main memory control unit (MCU) 1 from processing units such as a central processing unit (CPU) and a vector unit (VU) (not shown) In the priority cycle shown in Fig. a, the request is made when the access priority for all unit data constituting each block from the access port 10' is secured, and the access to the block is simultaneously executed by the main storage unit (MSU).
It was sent to

In this method, all unit data (called elements) of each access request are checked for all conflict conditions at the same time. '' is performed by each of the check units 11a to 11c, and then the priority control unit 11d determines the access request with the highest priority based on the result of the check, so that the access request with the determined highest priority can be transmitted. Therefore, an access request cannot be sent to the main storage unit (MSU) unless all of the conflicting conditions are cleared, especially when the number of conflicting conditions increases due to multiprocessorization, etc. However, there was a problem in that the transmission efficiency was greatly reduced.

For example, as shown in figure b, 4 elements (0
- 3) as one block, if elements 1 and 3 are bank busy in the priority cycle (cycle 1), all four elements making up the block will be waiting, and In the next priority cycle (cycle 2), even if elements 1 and 3 become accessible, if element 0 becomes bank busy based on the conditions of an access request from another processing device, then the block will still be accessed. All 4 elements are waiting, and this block starts from cycle 3 onwards.
Minimum bank busy cycles (e.g. 8 cycles for fetish, 12 cycles for store)
There was a problem with having to wait for a long time (cycles, etc.).

In view of the above-mentioned conventional drawbacks, the present invention has one or more main storage units (MSU), and has one or more processing units logically connected to the main storage units (MSU). A computer system having a main memory control unit (MCU) that controls whether one or more access requests can be sent to the main memory unit (MSU) per unit machine cycle, the main memory control unit (MCU) ) and the main storage unit (MSU) have one or more access request buses corresponding to unit data lengths, and access requests from the processing device to the main memory control unit (MCU) are made based on the unit data length or In a computer system in which data is transmitted (block access) with a data length corresponding to multiple times the unit data length, data is transmitted in order from the elements that can access the main storage unit (MSU) within the block, and the data is accessed from the main memory. The purpose of this invention is to provide a main memory access control method that improves the usage efficiency of a device (MSU).

[Means for solving problems]

The above problems are solved by a main memory access control method having the following configuration.

It has one or more main storage units (MSU),
1 logically connected to the main storage unit (MSU)
A computer system comprising a main memory control unit (MCU) that controls whether or not one or more access requests can be sent to the main storage unit (MSU) from one or more processing units per unit machine cycle, between the main memory control unit (MCU) and the main memory unit (MSU), an access request bus corresponding to one or more unit data lengths is provided between the main memory control unit (MCU) and the main memory control unit (MSU); ) In a computer system, an access request for 1 is sent with a data length corresponding to a unit data length or multiple times the unit data length (block access).
The block access to the main memory control unit (MCU) is divided into smaller access units corresponding to the unit data length, and an access request is sent to the main memory unit (MSU) for each unit data length. In the main memory access control method configured to arbitrarily control the transmission order within the block access, the main memory control unit (MCU) is provided with a main memory access control method corresponding to each segment of the main memory unit (MSU). A first priority cycle mechanism that performs a bus conflict check between the access ports that are connected to each other, and a second priority cycle mechanism that performs a bank busy check for unit data in each segment are provided. The cycle mechanism performs a conflict check between the buses provided corresponding to each access port, and the second priority cycle mechanism performs a bank busy check within the bus to determine if the bus is busy. The configuration is configured to send an access request for each unit of data to each bank, and a table is provided to manage the acquisition of priority for each unit of data from each access port in the second priority cycle. , Based on the priority acquisition information for each unit data in the management table, detects the completion of transmission of all unit data of a block consisting of a plurality of unit data from each access port, and determines that the block access is completed. Configure it to do so.

[Effect]

That is, according to the present invention, the output of the first access port of the main memory control unit (MCU), that is,
An access request consisting of one or more unit data is processed in the first priority cycle.
Checks for bus conflicts for each segment that makes up each main storage unit (MSU),
Check whether the second access port corresponding to each segment can be set.

Regardless of whether the access request set to the second access port in this cycle is for unit data or block data, there is no longer any conflict between buses, so in the second priority cycle, a bank busy check is performed. etc,
Only the competition condition within the segment is checked, and depending on whether the check is successful or not, it is determined whether to issue an access request to the main storage unit (MSU).

Also, in this cycle, a priority acquisition management table is provided, and based on the priority acquisition information for each unit data in the management table, the completion of transmission of all elements constituting each block is detected, and the Be aware of termination of access.

By controlling in this way, the access ports provided for each segment in the main memory control unit (MCU) are not made to wait due to contention conditions other than the relevant element, so if the access ports are in different banks. This enables transmission every cycle, which has the effect of increasing access efficiency to the main storage unit (MSU).

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention, FIG. 2 is a diagram explaining the operation of block access according to the present invention, and FIG. 3 is a diagram showing a priority acquisition management table according to the present invention. FIG. 2 is a diagram explaining the operation of the
The truth table of the code is shown, and access requests from each device in FIG. 1 are processed in two priority cycles: conflict check between buses and bank busy check within the bus. The means for checking and the means for recognizing the end of block access shown in FIG. 3 are necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The main memory access control method of the present invention will be explained below with reference to FIGS. 1 to 3.

Usually, a main storage unit (MSU) is divided into a plurality of segments (SEG), and a bus is provided corresponding to each segment (SEG).

Therefore, in the present invention, for access requests received from a plurality of processing devices at the first access port 10, the bus conflict check & other check section 11 first checks for conflict conditions between buses, and then prioritizes the access requests. The authorized access request is sent to the second access port 1 corresponding to each bus.
Set to 2.

As described above, the access request set to the second access port 12 is transmitted to the second access port 12.
Since we have obtained the right to use the bus corresponding to 2.
In the SEG bank busy check section 13,
If the priority within the bus, that is, the priority in the bank busy check, can be obtained, the data can be sent to the main storage unit (MSU) immediately.

In this figure, for example, this state is represented by “MS
G 0 MSU 0, SEG 0" etc.
That is, it shows that an access request can be sent to a specific bank in segment (SEG) 0 of the main storage device (MSU 0).

When controlled in this way, each main storage unit (MSU)
By corresponding to each segment, it becomes possible to independently issue an access request for each bank, for example, a unit data length of 8 bytes.

The transmission operation at this time will be explained with reference to FIG. 2. In the second priority cycle (cycle 1), the block access data for which an access request was received from a certain processing device is unit data (referred to as an element) 0. It is familiar from ~7,
When the bank busy state is canceled for the elements 0 and 2 (that is, the priority is acquired) and the call becomes possible {this is indicated by '0' and the bank busy state is indicated by 'x'], the corresponding In the second priority cycle (cycle 1), since there is no competition condition between banks, the access request that is cleared from the bank busy is immediately sent to the main storage unit (MSU).
sent to.

Then, in the next second priority cycle (cycle 2), when the bank busy state of elements 1 and 3 that were bank busy in the previous cycle is released, the unit data is transferred to the main memory in that cycle. (MSU).

As a result, in the next second priority cycle, a bank busy check is performed for the following elements 4 to 7, and data is sequentially sent to the main storage unit (MSU) starting from the unit data whose bank busy status has been cleared. be done.

Therefore, in a block access that is transmitted with a data length that is multiple times the unit data length, the plurality of unit data that make up the block will be transmitted independently, and the order will be affected. Therefore, it is necessary to recognize by some means the end of access to the block, that is, the end of transmission of the data block.

Therefore, in the present invention, the priority acquisition management table 14 shown in FIG. 3a is provided, and in the above second priority cycle,
When the priority is acquired for each access request from each second access port 12, '1' is sent to this management table 14.

In this example, block access will be explained using, for example, a 32-byte (hereinafter referred to as 32B) block, a 16-byte block, and an 8-byte block.

Therefore, in the case of 32-byte block access, the port OP code registers (B ₀ , B ₁ ) 140
is set to '11', so as is clear from the truth table in figure b, the AND circuit 14b is set to '1'.
Therefore, the AND circuit 15a is gated.

Here, when _the priority of the access request signal from the second access port 12 shown in _FIG . It is recognized that the transmission of the 32-byte block access request has been completed, and the AND circuit 15a is set to '1' via the OR circuit 14a.
is energized, and the logical sum circuit 16 outputs the management table 1.
Functions to reset 4.

To explain the above operation more specifically, in the OR circuit 14a, the above management table (E ₀
Since the output signal of ~E ₃ ) 14 and its input signal are logically summed, for example, the management table (E ₀ ~ _{E 2} ) (corresponding to elements 0 to 2) 14 is '1'. 'When the access request signal corresponding to element 3 is given priority in the next cycle, the output of the AND circuit 15a is transmitted through the OR circuit 14a in that cycle. 1', the OR circuit 16 immediately outputs a signal ``reset table'' that resets the management table (E ₀ to E ₃ ) 14, making it possible to recognize the end of block access in a cycle-based manner. .

It functions in the same way for 16-byte and 8-byte block accesses, and can recognize the end of each block access.

When the priority acquisition signal for the next access request is input from the second access port while the reset signal "reset table" is being output, the management table (E ₀ to _{E 3} ) is
14 is a set-priority flip-flop (FF)
Since the access request signal is configured as follows, the set operation based on the access request signal is given priority, and block access is managed without logical delay.

As described above, the present invention has one or more main storage units (MSU), and the main storage unit (MSU)
A main memory control unit (MSU) that controls whether one or more access requests can be sent to the main storage unit (MSU) per unit machine cycle from one or more processing units logically connected to the MSU. A computer system having one or more access request buses each corresponding to a unit data length between the main memory control unit (MCU) and the main memory unit (MSU), In a computer system, an access request from a device to a main memory control unit (MCU) is sent with a data length corresponding to a unit data length or multiple times the unit data length (block access). In priority cycle 1, main storage unit (MSU)
In the next cycle, a bank busy check is performed in the selected segment, even in the case of a block access request consisting of multiple units of data. The feature is that in each segment, accessible unit data can be sent to the main storage unit (MSU) every moment.

〔Effect of the invention〕

As described in detail above, the main memory access control method of the present invention allows block access from one or more processing devices to the main memory control unit (MCU) to be performed within the main memory control unit (MCU). Divide into smaller access units corresponding to the unit data length, send an access request to the main storage unit (MSU) for each unit data length, and arbitrarily control the order of sending within the block access. A main memory access control method configured as follows, wherein the main memory control unit includes a first priority check for bus conflicts between access ports provided corresponding to each segment of the main memory unit (MSU). A take cycle mechanism,
A second priority cycle mechanism that performs a bank busy check of unit data in each segment is provided, and the first priority cycle mechanism performs a conflict check between buses provided corresponding to each access port. The second priority cycle mechanism performs a bank busy check on the bus, and if the bus is not busy, an access request is made to each bank for each unit of data. The access port provided for each segment in the main memory control unit (MCU) does not have to wait due to contention conditions other than the relevant element, and if the bank is different, it is possible to transmit every cycle. This has the effect of increasing access efficiency to the device (MSU).

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing an embodiment of the present invention, FIG. 2 is a diagram explaining the operation of block access according to the present invention, and FIG. 3 is a diagram explaining the operation of the priority acquisition management table of the present invention. Figure 4 is a diagram explaining the conventional main memory access control method.
It is. In the drawing, 1 is a main memory control unit (MCU), 10 is a first access port, 10' is an access port, 11 is a bus conflict check & other check section, 11a is a bus conflict check section, and 11b is a bank busy check. Department,
11c is another conflict check section, 11
d is a priority control unit, 12 is a second access port, 13 is an SEG bank busy check unit, 14 is a priority acquisition management table (E ₀ to E ₃ ) or simply a management table, 140 is a port OP code register (B ₀ , B ₁ ), 14a is an OR circuit, 14b~ are AND circuits (32B, 16B,
8B), 15a~ show an AND circuit, and 16 shows an OR circuit, respectively.

Claims (1)

[Claims] 1. A unit machine cycle from one or more processing devices having one or more main storage units (MSU) and logically connected to the main storage units (MSU) A computer system having a main memory control unit (MCU) 1 that controls whether or not one or more access requests can be sent to the main storage unit (MSU), wherein the main memory control unit (MCU) 1 and the main storage unit (MSU) have one or more access request buses each corresponding to a unit data length, and access requests from the processing device to the main memory control unit (MCU) 1 are made based on the unit data length or In a computer system where data is transmitted (block access) with a data length that corresponds to multiple times the unit data length, the processing unit transfers data from the processing unit to the main memory control unit (MCU).
The block access to 1 is divided into smaller access units corresponding to the unit data length in the main memory control unit (MCU) 1, and the main memory unit (MSU) is accessed for each unit data length. A main memory control method for transmitting requests and arbitrarily controlling the order of transmitting within the block access, the method comprising A first priority cycle mechanism 11 that performs a bus conflict check between the access ports that are connected to each other, and a second priority cycle mechanism 13 that performs a bank busy check for unit data in each segment are provided. Priority cycle mechanism 11
Then, a conflict check is performed between the buses provided corresponding to each access port, and the second priority cycle mechanism 13 performs a bank busy check within the bus, and if the bus is not busy, each bus is checked. While transmitting an access request for each unit data to the bank, in the second priority cycle,
A management table 14 is provided to manage the acquisition of priority for each unit of data from each access port, and based on the priority information for each unit of data in the management table 14, a plurality of units of data from each access port are configured. A main memory access control method characterized in that the block access is determined to have ended by detecting completion of transmission of all unit data of a block.