JP2680208B2 - Memory access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control system, and in particular, it has a data transfer function for transferring a vector operation unit or a series of data spaces to another processor in addition to a single access from a CPU or the like. In a memory access control device that accepts block access from a data transfer unit etc., the type of each access, the busyness of the memory bank of each access destination,
Check address bus conflicts between each access,
The present invention relates to a memory access control device that selects executable access based on these results and sends it to a memory.

[0002]

2. Description of the Related Art Conventionally, access selection in a memory access control device for accepting a single access and a block access is performed by a method as shown in FIGS. In FIG. 6, the memory access control device 74 receives single access and block access from the data transfer device (MOVER) 71, the CPU 72, the vector operation unit 73, and the like. Then, the type determination unit 7
5, each of the bank busy check unit 76 and the bus conflict check unit 77 checks the type of each access, the busyness of the memory bank of the transmission destination of each access, the address bus conflict between the accesses, and the like, and uses these result data. For example, the priority of each access is determined by the procedure as shown in FIG. 7, and the address selector selects the address bus according to this priority to secure the bank memory of the transmission destination.
The memory is composed of memory units # 0 to # 7 such as a plurality of array cards.
Each of 7 is composed of n memory banks. Each memory unit and the memory access control device 74 are connected via a load address bus 81 and a store address bus 82, and a load data bus, a store data bus, etc. are connected to each memory unit. There is.

A single access is an access of, for example, 8 bytes that uses one address bus, and a block access is an access of a plurality of address buses, for example, a 64-byte access that uses 8 address buses. It is access. FIG. 7 is an explanatory diagram showing a procedure for determining the priority.

That is, for a certain access, it is checked whether or not the memory bank is "bank busy" based on the state of the busy flag relating to the memory bank of the access destination. Judge, and if “NO”, proceed to step.

It is judged whether or not an address bus conflict has occurred with another access, and "YE
If "S", the process proceeds to step, and if "NO", the process proceeds to step. Regarding the load instruction and the store instruction, it is judged whether the access of the other party of the address conflict is of the same type, and if “YES”, the process proceeds to step, and if “NO”, the process proceeds to step.

[0006] It is determined whether or not the predetermined priority order between single access and block access is high, and if "YES", the process proceeds to step "N".
If "O", proceed to step. It is determined whether or not the other party access due to the address bus conflict can be transmitted. If "YES", the process proceeds to the step, and if "NO", it is determined that "calling is impossible".

The priority of this access is determined. The priority of each access is determined by such a procedure.

[0008]

As described above, in checking the bank busy and the bus conflict in the conventional priority determination, the entire block width of the block access, that is, the address bus required for transmitting the block access and All of the destination memory banks are subject to judgment.

Therefore, for example, when only the memory bank 0 is "bank busy" for block access to the memory banks 0 to 7, the same kind of memory banks 0 to 7 (memory When a block access to units # 0 to # 7) and a single access with high priority are requested at the same time, the block access cannot be issued to the memory unit, and especially single access with high priority continues. However, there is a problem that the block access cannot be transmitted for a long period of time, and the throughput of the memory access at the source of the block access is reduced.

Therefore, in the present invention, the block access is divided into a plurality of divided block accesses, the divided block access is used as a unit to determine the priority with respect to the single access, and the divided block access having the priority is determined as follows. By transmitting in units, it is intended to increase the throughput of memory access of the block access request source.

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 1 denotes an access source, which sends a single access or a block access to a memory by a data transfer device (MOVER), a CPU, a vector operation unit, or the like.

A first access port 2 receives a block access and a single access. A second access port 3 receives block access and single access.

An access division unit 4 divides the block access accepted at the first access port into a plurality of, for example, two divided block accesses. However, whether or not to divide the received block access depends on conditions from other access sources. Reference numeral 5 denotes a bus conflict check unit, which checks a conflict state between single access, block access, and each divided block access.

Reference numeral 6 denotes a bank busy check unit which checks the state of the busy flag for the memory bank of the transmission destination of each access (block access, divided block access, single access). Reference numeral 7 denotes a priority determining unit that determines the priority of each access (block access, each divided block access, single access) by the same procedure as shown in FIG. Note that the priorities of conflicting accesses are determined in advance, and for example, block access has priority over block access and divided block access. Whether or not it is possible to issue block access, each divided block access, and single access from this priority determination unit (however, when the block access is “Yes”, each divided block access is No ”) is output.

Reference numeral 8 is a memory selection unit which selects an address bus corresponding to the access for which the output of the priority determination unit 7 is "OK". Reference numeral 9 denotes a memory, which is composed of, for example, memory units # 0 to # 7 each of which is composed of a plurality of memory banks, and an address bus is connected to each memory unit.

Here, the block access sent to the first access port 2 by the identification of the operation code is divided by the access dividing unit 4 into, for example, two upper divided block accesses and lower divided block accesses. . Then, the upper divided block access and the lower divided block access are sent to the bus conflict check unit 5 and the bank busy check unit 6 together with the single access and the block access, and in the former case, the "address bus conflict" between the single access and each block access. , And in the latter case, the "bank busy" of the destination memory bank for each single access and each block access is checked.

The priority determining section 7 includes a bus conflict check section 5, a bank busy check section 6
And the output of the first and second access ports 2 and 3, that is, the information about the above-mentioned "address bus conflict" and "bank busy", and a single access or block based on the opcode for the access accepted by each access port. Information such as access, load instruction or store instruction is supplied. Then, the priority of each access is determined based on these pieces of information.

[0018]

In the present invention, for example, the priority between access requesting devices is MOVER>CPU> vector operation unit, and for example, “single access from memory to memory bank 0 ” and “memory bank 0 from vector operation unit”. Block access to ~ 7 "
If and are accepted, this block access is MOVE
Single access from R, block access of vector operation unit with low priority,
Are divided into “divided block access to memory banks 0 to 3” and “divided block access to memory banks 4 to 7”, and the bank busy check unit 6 sends these four accesses to the memory banks. The bus conflict check unit 5 in parallel checks the address bus conflict between each of the three block accesses and the single access. Then, all of the memory banks 0 to 7 are not "bank busy", and both "single access to memory bank 0 " and "block access to memory banks 0 to 7" are related to the load instruction or the store instruction. If they are of the same type, the priority determining unit 7 determines the priority of each access according to the priority order between the single access and the block address. That is, "single access to memory bank 0 " and "memory bank 4"
Each of the accesses is transmitted to the memory by using the address bus 21 in the former and the address buses 25 to 28 in the latter.

In the above case, when memory bank 0 is "bank busy", "memory bank 4"
The "split block access to ~ 7" takes priority and uses the address buses 25-28 to issue this block access to memory.

As described above, since the block access is divided and accessed, for example, MOVE is performed.
When single access from R is continuously accessed, and the vector operation unit also performs block access continuously, the throughput for block access can be improved.

The above description is for the case where the load instruction address bus and the store instruction address bus are provided separately, but the present invention is also applicable when these address buses are commonly used. .

[0022]

Embodiments of the present invention will be described with reference to FIGS. In FIG. 2, reference numerals 31 to 34 are access ports for vector operation units, and 35 is a CPU or MOVER.
Access port, 36 to 37 are access dividing circuits, 3
8 to 39 are bus conflict check circuits, 40 is a bank busy check circuit, 41 is a priority determination circuit, 42 is a load instruction access selection circuit, 43 is a store instruction access selection circuit, and 44 are eight load instructions / store instructions each. Bus ports for the respective address buses, and 45 is a decoder for detecting that the access port 35 accepts single access. Therefore, the access division circuits 36 and 37 divide the block access and output the divided block access only when the access port 35 accepts the single access.

Here, a vector operation unit (not shown) having a plurality of vector operation units is connected to all of the vector operation unit access ports 31 to 34, and access from these vector operation units is possible. In the case of block access, one of the vector operation unit access ports 31 to 32 is entered, and in the case of single access, one of the vector operation unit access ports 31 to 34 is entered. The block access of the access ports 31 to 32 is performed by the access division circuit 3
MOV because it is a condition to enter 6 to 37 and divide again
Under the single access condition from the ER (the output of the decoder 45 is on), the opecode and address are decoded there to create signals for upper half block access and lower half block access.

Next, the bank busy check circuit 40 performs block access, upper half block access,
The bus conflict check circuit 3 is checked in parallel with the busy state of the destination memory bank of the four accesses of the lower half block access and the single access.
8 to 39, the bus conflict between each block access and single access is checked, and the priority determination circuit 41 determines the priority of each of the four accesses based on these results. At this time, the first bus conflict check circuit 38 performs block access from the access ports 31, 32 and access ports 33, 34, 3
5 is supplied with the single access from the access control circuit 5 to cause a bus conflict between the block access and the single access, and the second bus conflict check circuit 39 outputs the upper half block access and the lower half block output from the access dividing circuits 36 and 37. The access and the single access from the access port 35 are supplied to check the bus conflict with the access from the CPU or the MOVER.

When the priority of the single access is obtained, it is adopted as it is. For the block access from the access ports 31 and 32, the access having the highest priority among the three divided accesses is selected by the access selection circuit 42, 43, and subsequently these selected accesses are sent to the memory bank via the corresponding one of the bus ports 44.

FIG. 3 is an explanatory diagram showing an embodiment of the access division circuit. 51 is an opcode decoder, 52 is an address decoder, 53 is an access signal, 54 is a valid signal, 55 is an opcode, and 56 is a bank busy check. The flag 57 is an address. Opcode 5
5 contains information such as block access, single access, load instruction access or store instruction access. Here, the opcode decoder 51 receives the valid signal 54 and the opcode 55. If the opcode is a block access, the opcode decoder 51 changes the opcode to a half block access mode opcode based on the condition from the decoder 45. If it is not an access, the valid signal 54 for half block access is turned off. Further, the address decoder 52 modifies the address 57 to create an address for each half block access, for example, each start address.

When creating a divided block access such as 4 divisions or 8 divisions other than 2 divisions, a value that can be divided may be determined in advance and selected by an opcode. FIG. 4 is an explanatory diagram showing an embodiment of the access selection circuit. Here, from the priority determination circuit 41, the priority signal 61 for block access and the priority signals 62, 63 for half block access.
Is output. When the block access can be transmitted to the memory by taking the logical product of the former inversion signal and the latter signal, the half block access priority signals 62 and 63 are turned off.

FIG. 5 is an explanatory view showing the shortening of the access time according to the present invention, and it is premised that when the transmission is allowed in a certain machine cycle, the transmission is made in the next machine cycle. . That is, when the block access I using the buses 0 to 7 and the continuous single access IV with high priority come in, the block access becomes the time t ₈ at the time t ₈ in the conventional method of determining the priority only by the block access. While it is possible to send to the memory of block, block access I is set to upper half block access II and lower half block access II.
In the method of the present invention which divides into I and determines the priority including these half block accesses, the times t ₁ and t
₂ shows that upper half block access II and lower half block access III can be transmitted to the memory, respectively, and access time is reduced by 6τ.

[0029]

According to the present invention, in a memory control system for accepting a single access and a block access, first, a block access is divided into a plurality of, for example, two upper half block accesses and a lower half block access, and these four accesses are related. Bank busy and bus conflict are checked, and if access can be made in half block access units, this access is sent to the memory. The condition for creating half block access has a higher priority than its own access. Further, in the case of 8-byte access, it is possible to avoid a state where the own block access cannot be originated for a long period of time, and it is possible to improve the memory access throughput of the block access request source.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram showing an example of the present invention.

FIG. 3 is an explanatory diagram showing an embodiment of an access division circuit of the present invention.

FIG. 4 is an explanatory diagram showing an embodiment of an access selection circuit of the present invention.

FIG. 5 is an explanatory diagram showing shortening of access time according to the present invention.

FIG. 6 is an explanatory diagram showing a conventional access control method.

FIG. 7 is an explanatory diagram showing a procedure for determining the priority of each access.

[Explanation of symbols]

 1 Access Source 2 First Access Port 3 Second Access Port 4 Access Division 5 Bus Conflict Check 6 Bank Busy Check 7 Priority Determinator 8 Memory Selector 9 Memory 31, 32, 33, 34, 35 Access Port 36, 37 access division circuit 38, 39 bus conflict check circuit 40 bank busy check circuit 41 priority determination circuit 42 load instruction access selection circuit 43 store instruction access selection circuit 44 bus port 45 decoder 51 opcode decoder 52 address decoder 53 access Signal 54 Valid signal 55 Opcode 56 Bank busy check flag 57 Address 61, 62, 63 Priority signal 71 Data transfer device (MOVER) 72 CPU 3 spectrum calculation unit 74 address bus for memory access control apparatus 75 type determining unit 76 bank busy checking unit 77 the bus conflict checker 78 bus selection section 81 for loading the address bus 82 Store

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 61-286943 (JP, A) JP 1-99143 (JP, A) JP 61-153745 (JP, A) JP 4- 156632 (JP, A) JP-A-52-125243 (JP, A)

Claims (2)

(57) [Claims] 1. Access to a plurality of independently accessible memory banks is controlled in response to access requests from a plurality of access request devices that issue single access and block access requests. in the memory access control device, whether the access dividing means for dividing the block access request to the plurality of access requests, is accessed before each Kia access requesting device divided blocks requested by dividing by the access dividing means based on the priority of the A memory access control device comprising: access determining means for determining whether to perform block access as requested without division; and priority determining means for determining priority of each access request based on a predetermined condition. To 2. A condition that the access determination means determines whether or not to divide the block access, the memory access control apparatus according to claim 1, characterized in that so as not to split when there is no request for single access .