JPH02105251A - Intercommunication equipment for controller - Google Patents

Abstract

PURPOSE:To perform intercommunication by a single RAM by connecting an address bus and a data bus for plural CPUs to a RAM commonly, and prohibiting access by another CPU while either CPU makes access to the RAM. CONSTITUTION:It is judged whether or not a BUSY signal BE inputted from the CPU 1 for engine control via a first communication line 4 is 1, and when it is YES, a routine is completed while the CPU 1 for engine control makes access to the RAM 2, and when it is NO, a processing is progressed to the next step. The access to the RAM 2 is performed by setting a BUSY signal Br at 1, and also, outputting the BUSY signal Br to the CPU 1 for engine control via a second communication line 5. In other words, the readout of the control data of the quantity of injection of fuel, etc., from the RAM 2, or the write of the control data of a point of change gear, etc., on the RAM 2 is performed. When the access to the RAM 2 is completed, the BUSY signal Br is set at 0, and the BUSY signal Br is outputted to the CPU 1 for engine control via the second communication line 5.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a central processing unit (hereinafter referred to as CP) of a plurality of control devices.
The present invention relates to an intercommunication device for control devices that mutually communicates control data between the control devices (abbreviated as U).

<Prior Art> For example, in a car, in order to control engine fuel injection, ignition timing, or shift control of an automatic transmission,
A CPU is provided for each control, and by sharing the functions, it is possible to simplify the control of each CPU, improve efficiency, and shorten the execution time by parallel operation. Here, control data is mutually communicated between each CPU, and each CPU
The control data is made available to the PU.

For example, digital signals (High, L) are transmitted from an engine control CPU that controls fuel injection and ignition timing of the engine to a torque converter control CPU that controls an automatic transmission via multiple communication lines.

W signal) to communicate control data for fuel injection, etc., and select the optimal shift point to maintain optimal torque performance and fuel efficiency.

<Problems to be Solved by the Invention> However, in such conventional mutual communication devices, since mutual communication is performed using digital signals via multiple communication lines, there is a problem that the amount of information transmitted is small. be. Therefore, in order to share the information data between the engine control CPU and the torque converter control CPU and increase the amount of information transmitted, it is possible to use a dual port RAM.
There is a problem that the cost of AM becomes extremely high.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an intercommunication device that can significantly improve the amount of information transmitted at low cost.

<Means for Solving the Problems> For this reason, the present invention, as shown in FIG. In this case, the address buses B, , B connected to the address terminals of the respective central processing units A, , A are commonly connected to the address terminal of a single RAMC; The data buses D, , Dt connected to the data terminals of A, are connected to the data terminals of the RA.
A communication line E that is commonly connected to the data terminal of the MC and that communicates between the central processing units A, , A and the other central processing units A1 and A2 whether or not the RAMC is being accessed.
+ , Ez, and each central processing unit A
,,A2 is the other central processing unit A, ,A is the RAMC
determining means F for determining whether access is being made to the RAMC; , G2.

<Operation> In this way, when one of the central processing units is accessing the RAM, the RAM of the other central processing unit is accessed.
Access to M is stopped, and mutual communication between multiple central processing units is performed via a single RAM.

<Example> An example of the present invention will be described below with reference to FIGS. 2 to 4.

In FIG. 2, an engine control CPUI is provided that controls engine fuel injection and ignition timing.

The address bus IA of the engine control CPUI is RA.
The data buses IB of the engine control CPU are connected to the data terminals of the RAM 2, respectively.

In addition, the CPU 3 for controlling the torque converter controls the automatic transmission.
is provided. The address bus 3A of the torque converter control CPU 3 is connected to the address terminal of the RAM 2 in common with the address bus IA of the engine control CPU, and the data bus 3B of the torque converter control CPU 3 is connected to the data terminal of the RAM 2. They are connected in common to the data bus IB of the engine control CPU 1, respectively.

Further, the output port of the engine control CPU 1 and the human powered boat of the torque converter control CPU 3 are connected by a first communication line 4, and the engine control CPU 1 sends a BUSY signal Bt to the torque converter control CPU 3, which indicates whether or not it is accessing the RAM 2. is output via the first communication line 4.

Further, the output port of the torque converter control CPU 3 and the input port of the engine control CPU are connected by a second communication line 5, and the torque converter control CPU 3 sends a BUSY signal By to the engine control CPU that indicates whether or not it is accessing the RAM 2. is output via the second communication line 5.

The engine control CPUI operates according to the flowchart shown in FIG. 3 and accesses the RAM 2. Further, the torque converter control CPU 3 operates according to the flowchart shown in FIG. 4 and accesses the RAM 2.

Here, the engine control CPUI and the torque converter control C
The PU 3 is provided with a determining means and an access permission means, respectively.

Next, the operation of the engine control CPUI will be explained according to the flowchart shown in FIG.

In Sl, the second communication line 5 is connected from the torque converter control CPU 3.
It is determined whether or not the BUSY signal B7 input via the BUSY signal B7 is 1. If YES, the routine is terminated, and if NO, the routine proceeds to S2. Here, when the BUSY signal BT is 1, the torque converter control CPU 3 is accessing the RAM 2, and when the BUSY signal is B, the torque converter control CPU 3 is not accessing. Therefore, when the torque converter control CPU 3 is not accessed, the process proceeds to 32.

In S2, the BUSY signal is set in the B signal tube and is output to the torque converter control CPU 3 via the communication line 4 of the B signal tube 1. Here, BUSY signal BE=
1, the engine control CPUI is accessing the RAM 2, and when the BUSY signal is B, the engine control CPUI is not accessing the RAM2.

In S3, access to RAM2 is performed. That is, control data such as the fuel injection amount is written to the RAM 2, and control data such as the shift point of the torque converter control CPU 3 is written to the RAM 2.
Read from M2.

Then, when the access to RAM2 is completed, in S4, the BUSY signal B is set to the signal cylinder, and the BUSY signal B
The signal is output to the door conditioner control CPU 3 via the first communication line 4.

Next, the operation of the torque converter control CPU 3 will be explained according to the flowchart shown in FIG.

The Sll determines whether the BUSY signal input from the engine control CPU via the first communication line 4 is the B signal tube, and if YES, that is, the engine control? CPU for 11
If I is accessing RAM2, terminate the routine and select NO.
If so, the process advances to S12.

In S12, the BUSY signal BT is set to 1 and the BUSY signal B is output to the engine control CPU 1 via the second communication line 5.

In S13, access to RAM2 is performed. That is,
Control data such as the fuel injection amount is read from the RAM 2, and control data such as the shift point is written to the RAM 2.

When the access to RAM2 is completed, the BUSY signal B7 is set to 0 in S14, and the BUSY signal B7 is set to 0.
The signal is outputted to the engine control CPU 1 via the second communication line 5.

As explained above, the address buses IA, 3A and data buses IB, 3B of two CPUIs, 3 are commonly connected to RAM2, and one CPUI, 3
Check whether the other CPU is accessing RAM2.
communicate with each other via communication line 4.5, and each CPUI,
3 accesses RAM 2 while the other CPUs 1 and 3 are not accessing it, making it possible to communicate with each other using general RAM, which reduces costs and reduces the amount of information transmitted between each other. can be significantly improved.

Note that the present invention is also applicable to a case where there are three or more CPUs.

<Effects of the Invention> As explained above, the present invention connects the address buses and data buses of a plurality of CPUs to a RAM in common,
While one of the CPUs is accessing RAM, the other CPU
Since access by U is stopped, mutual communication can be performed using a single general RAM, which reduces costs and greatly increases the amount of information transmitted.

[Brief explanation of the drawing]

FIG. 1 is a diagram corresponding to claims of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are flowcharts of the same. 1... Engine control CPU IA, 3A...
Address bus IB, 3B...Data bus 2.
...RAM 3...CPU for torque converter control
4...First communication line 5...Second communication circuit Patent applicant Japan Electronics Co., Ltd. Agent Patent attorney Fujio Sasashima Figure 3, 4rm

Claims (1)

[Scope of Claims] An intercommunication device for control devices configured to mutually communicate control data between central processing units of a plurality of control devices, wherein an address bus connected to an address terminal of each of the central processing units is connected to a single address bus. The data bus connected to the data terminal of each central processing unit is connected commonly to the address terminal of one RAM, and the data bus connected to the data terminal of each of the central processing units is commonly connected to the data terminal of the RAM, so that the central processing unit connected by a communication line that informs the central processing unit of whether or not the RAM is being accessed, and each of the central processing units is connected to the R
a determining means for determining whether or not an access is being made to the AM; and a determining means for determining whether or not the AM is being accessed;
An intercommunication device for a control device, comprising: access permission means for permission to access an AM.