JPS6375867A - Ram controller using multi-cpu - Google Patents

Abstract

PURPOSE:To shorten waiting time by controlling a RAM time-division-wise by using a basic signal from a basic signal generation circuit and a read/write signal and a chip selecting signal from two CPUs. CONSTITUTION:The common RAM 13 is controlled time-division-wise alternately by the two CPUs 11, 12. Latch circuits 14, 20 to latch respective address data are inserted in the address buses of the CPUs 11, 12 and the RAM 13, and in their data buses, latch circuits 15, 19, 21, 25 to latch respective write data and read data. The basic signal generation circuit 26 generates a basic signal to let the respective CPUs 11, 12 alternately control the RAM 13 time-division- wise. A control signal generation circuit 27 generates a read/write control signal in accordance with the said basic signal and the read/write signal and the chip selecting signal from the respective CPUs 11, 12 so that the respective CPUs 11, 12 will alternately control the RAM 13 time-division-wise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a RAM control device using a multi-CPU that controls a common RAM by two CPUs.

[Prior Art] For example, there is a printer that uses two CPLIs, one CPU of which controls a print data editing system, and the other CPU controls a print operation system. In such a device, the RAM is commonly controlled by the two CPUs. Another example of this can be found in a facsimile machine in which the communication and compression processing system and the printer and line sensor control system are controlled by two CPUs.

Conventionally, such multi-CPU RAM system m+
As shown in Figure 4, the system is equipped with two CPUs 1.2,
That is, it is known that the CPUo 1 and CPUt 2 are connected to a common RAM 3 via a common address bus AB and a data bus DB, and each CPU01 and CPUt 2 exhibit RAM control shown in FIGS. 5 and 6, respectively. ing. That is, as shown in FIG. 5, the CPUa system first
Check whether the busy signal BSY1 from U52 is on, and if it is not on, the own busy signal BSY
It sets O, outputs it to CPUt, and waits for a predetermined time. Then, it is checked again whether BSYr from the CPU 1 is on, and if it is on, BSYo is lowered to return to the initial state, and if it is not on, processing on the RAM 3 is performed for the first time. When this process is finished, it lowers its own BSYO and ends the process.

On the other hand, the CPU1 system first uses CPUa as shown in Figure 6.
It is checked whether the busy signal @BSYa from 1 is on, and if it is not on, it sets its own busy signal BSY1, outputs it to CPUo, and waits for a predetermined time.

And CPU again.

Check whether BSYo is standing or not, and if it is, wait until it falls. If it is not standing, processing for RAM3 is performed for the first time.

When this process is completed, it lowers its own BSYl and ends the process.

[Problems to be Solved by the Invention] In such a conventional device, when the other party's CPU was controlling the RAM, it was necessary to wait until the other party's CPU finished controlling it.

For this reason, if this is applied to a printer, for example, when one CPU is editing data, the other CPU will not be able to print data, creating a problem that cannot be addressed if high-speed printing is required. there were.

This invention aims to shorten the time taken by two CPUs by controlling a common RAM alternately in a time-sharing manner, and is capable of increasing speed when applied to, for example, printers and facsimile machines. The purpose is to provide a RAM control device using a CPU.

[Means for Solving the Problems] This invention provides an R
AMII! 1] In the device, each CPU and RA
A latch circuit that latches the address data inserted into the address bus with M and a latch circuit that latches the store data and read data that are inserted into the data bus, respectively, and the control of the RAM by each CPU in a time-sharing manner. A basic signal generation circuit generates a basic signal for alternating the operation, and each CPU uses the basic signal from this basic signal generation circuit and the read, write, and chip select signals from each CPU to cause the RAM to be executed alternately in a time-division manner. The device is equipped with a control signal generation circuit that generates read and write control signals.

[Function] In the present invention having such a configuration, read and write control signals for the RAM are generated using the basic signal from the basic signal generation circuit and the read, write and chip select signals from the two CPUs, and the RAM is operated. Control is performed alternately in a time-division manner.

The data to be written to the RAM and the data read from the RAM are each latched in a latch circuit, and
The address bus and data bus connecting M and each latch circuit can also be shared in accordance with time division control.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is one CPU o 112 is the other C
PLIt, 13 is a RAM. An address bus ABn is connected from the CPU 011 to the input side of the latch circuit 14, and also to the input side of the latch circuit 15 and the buffer 16.
A data bus DBa is connected to the output side of the data bus DBa. The output side of the latch circuit 14 is connected to the RAM 13 via a buffer 17 and an inner address bus IAB.

The output side of the latch 15 is connected to the RAM 13 via a buffer 18 and an inner data bus IDB. Further, the inner data bus IDB has a latch circuit 19.
It is also connected to the input side of. The output side of this latch circuit 19 is connected to the data bus DBO via the buffer 16.

An address bus ABr is connected from the CPUt12 to the input side of the latch circuit 20, and a data bus Do1 is connected to the input side of the latch circuit 21 and the output side of the buffer 22. The output side of the latch circuit 20 is a buffer 23
and the RA via the inner address bus IAB.
Connected to M13. The output side of the latch 21 is connected to the RAM 13 via a buffer 24 and the inner data bus IDB. The inner data bus IDB is also connected to the input side of the latch circuit 25. The output side of the latch circuit 25 is connected to the data bus DBr via the buffer 22.

26 is a basic signal generation circuit, and this circuit is connected to each CPUo 1.
1. By inputting the E signal used in the CPUr 12, the basic signal CK shown in (a) to (e) in FIGS. 2 and 3 is generated.
Mouth, CKI, CK2, CKIB, CK2 B, C
Kt B and CK2 B are generated.

27 is a read that controls the RAM 13 alternately in a time-division manner;
This circuit 27 is a control signal generation circuit for generating a write control signal, and is composed of a circuit section 27a that generates a CPLIa-based control signal and a circuit section 27b that generates a CPLII-based control signal.

The circuit section 27a is 3ff! it's D type Fritzbuf O
It is composed of a plurality of inverters and gate circuits, and receives a chip select signal C8o and a read signal RDa from the CPUo11.

It receives the write signal WRa, and also receives the signals CKt, CKI B, and CKI B from the basic signal generation circuit 26, and outputs the control signals QIW and Qt R. The circuit section 27b is composed of three D-type flip-flops 31, 32, and 33, as well as a plurality of inverters and a gate circuit, and receives a chip select signal C5I, a read signal RD1, and a write signal WR from the CPU 112.
1 is input, and the signal @C is input from the basic signal generation circuit 26.
It inputs K2, CK2 B, and CK2 B and outputs control signals Q2 W and Q2 R.

Then, the control signal QIW is sent to an OR gate circuit 3.
4 to the RAM 13 as a write signal, and also to the buffer 118 as a control signal. Further, a control signal QsR is supplied to the RAM 13 as a read signal via the OR gate circuit 35, and is also supplied to the latch circuit 19 as a control signal. Further, the control signal Q2W is supplied to the RAM 13 as a write signal via the OR gate circuit 34, and is also supplied to the buffer 24 as a control signal. Further, the control signal @Q2R is supplied to the RAM 13 as a read signal via the OR gate circuit 35, and is also supplied to the latch circuit 25 as a υ control signal.

Signals C8o and RDa of the CPU011.

W Ro is supplied to the gate circuit 34 and the gate circuit 34
outputs a control signal for the latch circuit 14 from C8 and outputs a control signal for the latch circuit 14 from C8.
a, WRg is supplied to the gate circuit 35 and the gate circuit 3
5 outputs a control signal for the latch circuit 15, and further supplies signals C8O and RDg to a gate circuit 36, which outputs a control signal for the buffer 16.

The signals @C8t, RDt, and WRI of the previous &ICPUt12 are supplied to the gate circuit 37, and the control signal of the latch circuit 20 is output from the gate circuit 37, and the signals @C8t, WRl
is supplied to the gate circuit 38, and the gate circuit 38 outputs a control signal for the latch circuit 21, and furthermore, the signals C8t,
RDt @Goo8 Supplied to circuit 39 and its gate circuit 39
A control signal for the buffer 22 is output from the buffer 22.

In this embodiment with such a configuration, for example, one C.
When writing to the RAM 13 is controlled by PUoll, it is performed at the timing shown in FIG. That is, the basic signal generation circuit 26 generates the signals CKo, CK1 . CK2, CK
CPLIOI while t B, CK2 B is occurring.
Assuming that the chip select signal C3O is outputted from I at the timing shown in (a) in FIG. 2, and then the write signal WRa is outputted at the timing shown in (f) in FIG. 2, the flip-flop 29 operates. Then, the signal @QWo is output from the Q output terminal at the timing shown in FIG. 2 (h). In this state, when the signal CK1 input to the 7 flip-flop 30 rises, the flip-flop 30 operates and the signal Q1 is output from its Q output terminal at the timing shown by (+) in FIG. Then, the signal QIW is outputted from the circuit section 27a at the timing shown in (k) in FIG. 2, and the write signal W shown in (1) in FIG.
R will be supplied.

The CPUo also controls the address bus ABO and the data bus DBo at the timing shown in (m) in FIG. 2, and sends an address to the latch circuit 14 as shown in (n) in FIG. and causes the latch circuit 15 to latch the data. Then, at the timing when the signal CK1 is supplied to the buffer 17, the inner address bus IA is connected as shown in (1) in FIG.
B is controlled to transfer the address from the latch circuit 14 to the RAM 13.
At the same time as the signal QIW is supplied to the buffer 18, the inner data bus IDB is controlled and data is transferred to the latch circuit 15 as shown in (0) in FIG.
The data is supplied to the RAM 13 from there. Of course, at this time, the write signal WR is supplied to the RAM 13 at the same timing.

In this way, the CPUall writes data to the RAM 13 at the timing when the signal CKI is generated immediately after the write signal WRa is output without waiting time. Then, at the next timing when the signal CKI is generated, the CPU 212
The RAM 13 is controlled by this.

Note that the signal Q! from the flip-flop 30! When the signal CLRa falls, the signal CLRa is generated to reset the flip-flops 28 and 29, as shown in FIG. 2(j). Furthermore, the flip-flop 30 is reset by the signal CKIB from the basic signal generation circuit 26.

Further, for example, when one CPU oll controls reading from the RAM 13, it is performed at the timing shown in FIG. 3. That is, from the basic signal generation circuit 26 to the third
At the timings shown in (a) to (e) in the figure, the signal CKo,
CKt, CK2.

CPU01 while CKIB, CK2 B is occurring.
Suppose that the chip select signal C8o is outputted at the timings shown by (Q) in FIG. 3 from 1 to 3, and then the read signal RDo is outputted at the timing shown in (f) in FIG.
The flip 70 knob 28 operates and the signal QRO is output from its Q output terminal at the timing shown in (11) in FIG. In this state, when the signal CK1 input to the flip-flop 30 rises, the seven flip-flop 30 operates and the signal Q1 is output from its Q output terminal at the timing shown in FIG. 3(i). Thus, the signal QIR is output from the circuit section 27a at the timing shown in (j) in FIG. 3, and the read signal RD is supplied to the RAM 13.

The CPUa also controls the address bus ABO at the timing shown in (1) of FIG. 3, and activates the latch circuit 1 at the timing of outputting the read signal RDa as shown in (m) of FIG.
4 to latch the address. Then, at the timing when the signal MCKt is supplied to the buffer 17, the inner address bus JAB is controlled to supply the address from the latch circuit 14 to the RAM 13 as shown in (n) of FIG. Then, with a slight timing delay, the inner data bus TDB is controlled as shown in (0) of FIG. 3, data is read from the RAM 13, and is latched into the latch circuit 19 at the timing of (p) in FIG. The data latched in the latch circuit 19 is stored in the time buffer 1 indicated by (Q) in FIG.
6 to read the data.

In this way, data reading from the RAM 13 by the CPUoll begins with the output of the read signal RDo and then the signal CK1.
The processing is delayed by one cycle of waiting time. Then, at the next timing when signal CK1 is generated, CP
The RAM 13 will be controlled by U212.

Note that when the signal Q1 from the flip-flop 30 falls, the signal CLRo is generated as shown in FIG. 3(k) to reset the flip-flops 28 and 29. Furthermore, the flip-flop 30 is reset by the signal CKIB from the basic signal generation circuit 26.

In this way, RA by 010guchi11 and CPUn11
M13 is performed alternately in a time division manner based on the cycle of the signal CKt, and when data is written to the RAM 13, it is performed without a waiting time, and when data is read from the RAM 13, it is performed with a waiting time of only one cycle of the signal CKI. CPUoll and CPUt can each control the RAM 13 without waiting for a long time. Therefore, if this is applied to a printer, CPUn
11 controls the data editing system, and CPUn11
If the printing operation system is controlled in step 2, a high-speed printing operation is possible in which data can be printed while editing the data.

[Effects of the Invention] As described in detail above, according to the present invention, in a device where two CPUs control a common RAM, it is possible to reduce the time taken by each CPU, and it is applicable to, for example, printers and facsimile machines. In this case, it is possible to provide a RAM control device using multiple CPUs that can speed up printing and transmission.

[Brief explanation of the drawing]

Figures 1 to 3 show embodiments of this invention.
The figure is a circuit diagram, Figure 2 is a timing waveform diagram showing the operation timing of each part when data is written by one CPU, and Figure 3 is a timing waveform diagram showing the operation timing of each part when data is read by one CPU. Figures 4 to 6 show conventional examples, where Figure 4 is a block diagram, Figure 5 is a flowchart showing RAM t211 by one CPU, and Figure 6 is RAM fril by the other CPU.
1 is a flowchart showing l m. 11...CPU port, 12...CPU1.13...
・RAM, 14.15, 19.20, 21.25...
Latch circuit, 26... Basic signal generation circuit, 27...
Control signal generation circuit.

Claims (1)

[Claims] In a RAM control device that controls a common RAM between two CPUs, a latch circuit that latches address data inserted into the address bus of each of the CPUs and the RAM, and write data and data inserted into the data bus, respectively. a latch circuit that latches read data; a basic signal generation circuit that generates a basic signal for causing each of the CPUs to control the RAM alternately in a time-sharing manner;
Control in which each CPU generates read and write control signals that control the RAM alternately in a time-sharing manner based on the basic signal from this basic signal generation circuit and the read, write, and chip select signals from each of the CPUs. A RAM control device using a multi-CPU, characterized by comprising a signal generation circuit.