JPS58225421A - Data processor - Google Patents

Abstract

PURPOSE:To ensure access at a high speed regardless of the difference of the access timing time, by giving both writing and reading accesses to an input/ output device independently of a microprocessor. CONSTITUTION:Both writing and reading accesses are given to an input/output device independently of a microprocessor. For instance, a data receiving interruption signal SRINT is supplied to a timing controller 7 from an input/output device 2. Then the signal RINT is supplied to a microprocessor 1 via a controller 3. An I/O instruction is transmitted from the processor 1 to reset an interruption, and a selection signal SEL is sent to a timing controller 6 and command data 4 from a device coder 5. Then a signal CRST is transmitted from the coder 4. An I/O instruction is transmitted from the processor 1 to read out the contents of a buffer 9. Then the processor 1 transmits an access timing signal IORQ.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a data processing device equipped with a special data input/output control access method.

In particular, the present invention relates to a data processing device that performs special data input/output control access when the access timings of a microprocessor and an input/output device connected thereto are different.

(Description of Prior Art) Conventionally, in a data processing device using a microprocessor, the access timing time of an input/output device connected to a bus included in the microprocessor may differ from the access timing time of the microprocessor. be.

In such cases, the microprocessor waits to match the access time of the input/output device.

Alternatively, the microprocessor operation is stopped until the input/output device access is completed by providing a hold (Wait or [(old)) function.Therefore, the access timing of the input/output device is determined by the microprocessor's access timing. If it is significantly longer than the timing time, the processing of the microprocessor will stop for that period, resulting in a reduction in the processing ability of the microprocessor.

(Object of the Invention) The object of the present invention is to connect a microprocessor and an input/output device via a reading sofa and a writing sofa,
Write access and read access are performed to the input/output device independently of the microprocessor, and when reading data, an interrupt is generated to the microprocessor by inputting data to the read buffer, thereby allowing access between the microprocessor and the input/output device. An object of the present invention is to provide a data processing device that can perform high-speed access without being affected by timing differences.

(Description of structure and operation of the invention) A data processing device according to the invention includes a microprocessor,
input/output device and command decoder.

The device includes a device decoder, a read buffer, a write buffer, one interrupt controller, and first and second timing controllers.

A microprocessor has an address bus, a data bus, and a control bus, and has an interrupt function.
It is something that you have. The input/output device has means for realizing an interrupt function. The command decoder f is used to decode commands on the address bus and obtain commands. The device decoder is for decoding device information on the address bus to determine the I10 device address. The read buffer is used to temporarily hold data from the input/output device before sending it to the data bus.

The write buffer is used to temporarily hold data on the data bus before sending it to the input/output device. An interrupt controller is connected to the microprocessor and is for controlling interrupts. 1st timing control) o
The controller is used to capture the timing at which data is written to the microprocessor and to perform write access to the input/output device independently of the microprocessor. The second timing controller captures the timing of the receiving interrupt from the input/output device, provides read access to the input/output device independently of the operation of the microprocessor, and controls the microprocessor by inputting data to the read buffer. It is used to generate an interrupt to the processor.

(Description of Embodiments) Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of one embodiment for realizing a data input/output access method according to the present invention, and FIG.
The figure is a circuit diagram of the first and second timing controllers in FIG. 1.

In FIG. 1, l is a microprocessor, 2 is an input/output device that operates at low speed, 3 is an interrupt controller that controls multiple interrupts from the input/output device, and 4 is a command for decoding the I10 command from the microprocessor. decoder.

5 is a device decoder for selecting the I10 device of the input/output device; 6 is a first timing controller for controlling timing according to a control signal from the microprocessor; 7 is an interrupt from the input/output device 2; and a second timing controller for performing control depending on the activation designation from the first timing controller 6; 8 is a first driver having a tri-state output; 9 is a read buffer for reception; The trusted write buffer, 11, is a second driver with a tri-state output. Also, in FIG. 2, 12 is the first A
ND gate, 13 is a NAND gate, 14 is an OR gate, 15 is an R8 type 7 flip-flop, 16 is a 4-person first D type flip-flop, 17 to 19 are second to fourth flip-flops.
AND gate 20 is a second D-type flip-flop operated by one person. In FIG. 1, microprocessor 1
are the data bus included in the microprocessor 1 and the first
It is connected to the input/output device 2 via a driver 8 and a read buffer 9. Further, the microprocessor 1 is connected to the input/output device 2 via a data bus included in the microprocessor 1, a write buffer IO, and a second driver 11. When the microprocessor 1 receives data from the input/output device 2, the input/output device 2
A data reception interrupt signal $RINT is applied to the second timing controller 7 from the data reception interrupt signal $RINT. In the second timing controller 7, $R input via the OR gate 14
The R8 type flip-flop 15 is set by the INT signal, and the first D type flip-flop 16, which operates as a stage counter, is operated. When the signal PRET turns on after four clocks of the input clock φ, the R8 type flip-flop 15 is reset. At this time, the first D-type flip-flop 16, which operates as a stage counter, receives the access timing signal $l0RQ of the input/output device 2.
is generated, and the fourth AND gate 19 generates a signal $RD indicating read. At this time, a signal $RD is applied to the input/output device 2 to perform a read operation. The read data is set in read buffer 9 by signal $l0RQ, and at the same time, second D-type flip-flop 20 for interrupt is set. As a result, a signal HINT is sent from the second timing controller 27, and an interrupt signal INT is sent to the microprocessor l via the interrupt controller 3.

The microprocessor l that receives the interrupt sends an I10 instruction to reset the interrupt.

The selection signal S of the input/output device 2 is output by the device decoder 5.
EL is sent out and decoded by the command decoder 4 to become the signal 0R8T, which is sent to the second D-type flip-flop 2.
0 is reset. Furthermore, the microprocessor 1 has an I1 for reading the contents received into the read buffer 9.
0 command is also sent. Therefore, the I10 access timing signals l0RQ and RD are transmitted to the first timing controller 6.
given to. At this time, the AND condition of the first AND gate 12 in the first timing controller 6 is satisfied and the signal RDE rises.

The contents of the read buffer are output to the data bus via the first driver 8 and received by the microprocessor 1. When transmitting data from the microprocessor 1 to the input/output device 2, when a data transmission request interrupt signal $8INT is generated from the input/output device 2, an interrupt is generated in the microprocessor 1 via the interrupt controller 3.

When the microprocessor 1 determines that it is a data sending interrupt, it sends an I10 command to send the sending data to the write buffer 10. At this time, the device decoder 5 receives the selection signal SF! for the input/output device 2! L rises, and the access timing signals l0RQ and WO are applied to the first timing controller 6. Therefore,
NAND gate 13 of first timing controller 6
When the logical product condition is satisfied, the set-tie signal WDS of the write buffer 10 is applied to the write buffer 10, and the transmission data from the microprocessor 1 is written into the write buffer 10. At the same time, the second timing controller 7 outputs R8 via the OR gate 14.
A type flip-flop 15 is set and 1. A first D-type flip-flop 16 operates as a stage counter. Therefore, the signal FR8T rises after four clocks of the input clock φ, and the R8 type flip-flop 15 is reset. Next, the access timing signal $l0RQ of the input/output device 2 is generated by the first D-type flip-flop 16 which operates as a stage counter, and the access timing signal $l0RQ of the input/output device 2 is generated.
ND gate 18 generates a signal $WD indicating writing.

These signals are given to the input/output device 2. At this time the second
AND game) 17, the logical product condition is satisfied and the signal WDB
At startup, the contents of the write buffer 10 are applied to the data input terminal of the input/output device 2 via the second driver 11, and the transmission data from the microprocessor 1 is written to the input/output device 2.

(Detailed Description of the Invention) As described above, the present invention provides a method for connecting a data bus from a microprocessor to an input/output device through a read buffer and a write buffer, and to connect the data bus from a microprocessor to an input/output device independently of the operation of the microprocessor. Write access and read access are performed on the input/output device, and when reading data, the data is read out (stored temporarily in the sofa and generated an interrupt to the microprocessor, so that the data can be read out at high speed without interrupting the processing of the microprocessor. This has the advantage that a high-speed data processing device can be realized with relatively low-speed and small-scale hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing apparatus according to the present invention, and FIG. 2 is a diagram showing the circuit block configuration of the first Th and second timing controllers shown in FIG. 1... Microprocessor 2... Input/output device 3
...Interrupt controller 4...Command decoder 5...Device decoder 6.7...Timing controller 8.11...Driver 9...Read buffer 1
0...Write buffer

Claims (1)

[Scope of Claims] A microprocessor equipped with an address bus, a data bus, a control node, and an interrupt function; an input/output device equipped with means for realizing the interrupt function; a command decoder for decoding the above command; a decoder decoder for decoding the device information on the address bus to determine the I10 device address; a read buffer for temporarily holding data to be sent; and a write buffer for temporarily holding data to be sent from the data node to the input/output device. An interrupt controller for controlling the interrupt function is connected to the -f microprocessor, and an interrupt controller is connected to the microprocessor to capture the timing when the microprocessor writes data to the write data (sofa) and performs the input/output operation independently of the microprocessor. The first one for write access to the device.
The timing controller 2 of the microprocessor captures the timing of a reception interrupt from the input/output device to the microprocessor, performs read access to the input/output device independently of the operation of the microprocessor, and stores data in the read buffer. a second timing controller 2 for generating an interrupt in the microprocessor in response to an input of the data processing apparatus.