JPS5858632A - Controlling method of input/output interface - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by simple constitution, by directly switching an address or a command as hardware by a control signal from an input/output device controlling part. CONSTITUTION:An address or a command is switched directly as hardware by a control signal from an input/output device controlling part. For instance, an address signal is sent out to a decoder part 6 of an input/output device interface 2, an input/output device controlling part 7 and a storage part 4 through an address bus from a CPU 1, and also a control signal is sent out to the decoder part 6 and the input/output device controlling part 7 through a control bus. Subsequently, a select signal is sent out to the input/output device controlling part 7, a buffer part 5 and the storage part 4 from the decoder part 6. Subsequently, a control program of an input/output device 3 is switched as hardware by sending out a control signal to the storage part 4 from the input/output device controlling part 7.

Description

[Detailed Description of the Invention] The present invention comprises a CPU (central control unit) and 1, 10 (input/output)
Control method for the % interface between the device and the device % type % In conventional general % interfaces, the data transfer method between the CPU and the % device is a program transfer method in which everything is controlled by the CPU, and a program transfer method in which everything is controlled by the CPU, and a storage section that transfers data without CPU intervention. and the % device directly exchange data D
M A (DirectMemory Accesses
s) Transfer method is used0 For example, in data transfer between a CPU and a floppy disk device, the former method is used to transfer data to an 8-inch single density drive or a 5.25-inch single density drive when the data transfer speed of the CPU is low. The limit is to use it against 562
The latter method is used for 5-inch double-density drives and 8-inch double-density drives. However, this latter method is circuit-complicated and expensive.

To explain in more detail, in the former program transfer method, all data is sent and received with the intervention of the CPU.
% Receive the data transfer preparation completion status of the device, judge it, and jump to the appropriate routine, all of which must be done using commands on the software, and on a slow CPU, the execution time of the instruction will be long\ %device This method has the disadvantage that it cannot meet the required transfer time.

On the other hand, the latter DMA transfer method requires a dedicated and expensive MA controller, is circuit-complicated, and has a complicated circuit because the DMA controller transfers data directly to the storage unit without data transfer via the CPU. It was difficult to understand and confirm.

The present invention has been devised in view of these points, and provides a control system for 10 interfaces that has a simple configuration and is capable of transferring data at high speed.

The present invention will be described below with reference to embodiments shown in the drawings. 1st
The figure shows a block diagram of the % interface according to the present invention, and FIG. 2 shows a flowchart for explaining the operation of the interface. In FIG. 1, l is the CPU of the host computer.

2 is 1/interface, 3 is % device, where %
The interface 2 includes a storage section 4, a buffer section 5, a decoder section 6, and a percentage control section 7. In the interface 2, a control program is written in the storage section 4 in advance. Then, the inputs AK-1 to A of the storage unit 4 and the address bus of KCPUI are connected,
Further, the control signal output of the control section 7 to the input AK is connected. Further, a select signal from the decoder 6 is input to the storage section 4, the buffer section 5, and the % control section 7.

Now, to explain the operation of the control program of the device 3 according to the flowchart shown in FIG. 2, this program starts and when the data transfer preprocessing of the device 3 is completed, the address (AN...AK-) 11A
Jump to K@...Ao). This address contains an instruction to jump to its own address [JP(AN...AK+IIA)
KI...Ao)) is written.

On the other hand, the address (AN...AK-1-1tAK...A
o) contains an instruction [JP(A
N...AKL.

(',,,...6;),l are written. Here, when the %device 3 is preparing for data transfer, the control signal from the %control unit 7 remains AK, so the command (JP(AN・AK+,,AK,・Ao)) is repeated.
□Execute the wait loop. Then, soon when the first device 3 is ready for data transfer, the control signal from the second control unit 7 changes from AK to AK and the command (J P (A N -A K+, +AK・"A6)) is issued.
, and further executes the command (J P (A N-A K
ICK, . . . co)] and jumps to the data transfer routine (B), where CPU 1 transfers 1 byte of data. After this, when the control signal of the control unit 7 returns from AK to AK, the data transfer routine (5
), but since the same program is written in both transfer routines (B), the operation is hindered, and in the end, the address (AN...AK+1 .AK-...Ao) is reached.

Data transfer between the CPU 1 and the device 3 is completed by sequentially repeating the above sequence until the data to be transferred is completed.

In the above embodiment, the address is directly switched by the control signal from the % control unit 7, but the address may be switched.

As described above, according to the control method of the present invention, addresses and commands are directly switched in accordance with the control signal from the control section, so data transfer is performed as in the conventional program transfer method. This eliminates the need for software commands to receive and judge the readiness status and jump to the appropriate routine, reducing instruction execution time and meeting the transfer time required by the single device.

With the control method of the present invention, the operating clock frequency is 2MH
A % interface that enables data transfer between the Z CPU and the 5.25 inch double density drive is realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a % interface according to the present invention, and FIG. 2 is a flowchart for explaining the control operation of the embodiment. 1...CPU, 2...I10 interface, 8.
...% device, 4...storage section, 7...% control section. Agent Patent Attorney Aihiko Fukushi

Claims (1)

[Claims] 1. The address bus (or data bus) of the storage section in which the control program of the 1/10 device is written.
% control section Karanoko Z)'l: Supply the I-L signal and switch the execution address (or command) of the control program of the I10 device node-wise according to the logic value of the control signal, and control the CPU and % device. % interface control method characterized by matching operation timing.