JPH06236338A - Data input/output processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a program and to shorten the processing time by supplying addresses, selected so that an address line is substantially zero, and the decoding result of a read/write control signal to an output signal processing means. CONSTITUTION:The program on a CPU 10 inputs information on the operation of a switch, etc., corresponding to an address signal S16 to the CPU 10 as a data bus signal S15 from an input signal processing part 13 through diodes 12a-12n and a two-way data bus 15. Control information is outputted from the data bus 15 to a signal processing part 11 with an acknowledgement pulse signal (R/D) S18 generated by decoding an address signal S16 and a read/write(R /W) signal S17 corresponding to the inputted program and the program. A write pulse signal (W/R) is outputted from a decoder 14 with the data inputted to the CPU 10. A control information signal is outputted to the output signal processing part 11 only for a period wherein the write pulse signal is outputted, and then sent out of the output signal processing part 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output processing device in which a central processing unit reads operating states of switches and the like through a bidirectional data bus and outputs a control signal to an output signal processing unit of the device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional data input / output processing device. In FIG. 3, in this example, a CPU 20 that controls this apparatus, an output signal processing unit 21 to which a control information signal for switching a switch and the like is input, a buffer 22, and an input signal from the switch are supplied. Input signal processing unit 23 and decoder 24
And a bidirectional data bus 25.

Next, the operation of this conventional configuration will be described. FIG. 4 is a timing chart showing processed signals in the configuration of the conventional example. 4, in the data capture mode processed by the CPU 20, the address information S26 and read / write (R / R) shown in FIGS.
W) The signal S27 is input to the decoder 24. From the decoder 24 to the permission pulse signal (R / D) S shown in FIG.
28 is output. The CPU 20 fetches the information of the input signal processing unit 23 corresponding to the address by the program from the bidirectional data bus 25 as the data bus signal S25 only during the period in which the permission pulse signal S28 is output.

In the output mode in which the CPU 20 processes, as shown in FIG. 4E, a write pulse signal (W / R) is output from the decoder 24 according to the data taken in by the CPU 20.
Outputs S29. The control information signal is output to the output signal processing unit 21 only during the period when the write pulse signal S29 is output, and the control information signal is sent from the output signal processing unit 21.

Instead of supplying this address information to the input signal processing section 23, the same processing can be performed using the output port of the CPU 20.

[0006]

However, the conventional data input / output processing device has the problem that the circuit scale and cost increase because the buffer 22 is used.

Further, when the output port of the CPU 20 is used instead of the address information, there is a problem that the program capacity is increased and the processing time cannot be shortened.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent data input / output processing device capable of reducing the circuit scale and the program capacity and processing time.

[0009]

In order to achieve the above object, a data input / output processing device of the present invention comprises an output signal processing device connected to a bidirectional data bus connected to a central processing unit for program operation. , The input signal processing means connected to the bidirectional data bus through a diode and connected to another address different from the address used by the output signal processing means, and the address line used by the input signal processing means are substantially zero. A decoding means for giving the address selected as described above and the decoding result of the read / write control signal to the output signal processing means is provided.

[0010]

In the data input / output processing device of the present invention having such a structure, the input signal processing means is connected to the bidirectional data bus through the diode and is connected to another address different from the address used by the output signal processing means. To be done. Further, since the address selected so that the address line used in the input signal processing means becomes substantially zero and the decoding result of the read / write control signal are given to the output signal processing means, the information of the input signal processing means is provided. It eliminates the need for capture enable pulses and conventional buffers.

When the same processing is performed using the output port of the central processing unit, the step of operating the output port is omitted. Therefore, the circuit scale can be reduced, and the program capacity and processing time can be reduced.

[0012]

Embodiments of the data input / output processing apparatus of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data input / output processing device of the present invention. In FIG. 1, in this example, a CPU 10 that controls the apparatus,
An output signal processing unit 11 to which a control information signal for switching such as a switch is input, and diodes 12a and 12n
And an input signal processing unit 13 to which an input signal from a switch (not shown) is supplied, a decoder 14, and a bidirectional data bus 15. The CPU 10 operates according to a program, is connected to the input signal processing unit 13 through the output signal processing unit 11 and the diodes 12a and 12n by the bidirectional data bus 15, and is connected to the input signal processing unit 13 and the decoder 14 by the address signal S16. There is.

Next, the operation of the configuration of this embodiment will be described. FIG. 2 is a timing chart showing processed signals in the configuration of the embodiment. In FIG. 2, in the data acquisition mode processed by the CPU 10, as shown in FIG.
As shown in (b), the information of the operation of the switch or the like corresponding to the address signal S16 is transferred from the input signal processing unit 13 to the diodes 12a and 12n by the program of the CPU 10.
And the data bus signal S1 through the bidirectional data bus 15.
5 is taken into the CPU 10.

An enable pulse signal (R / D) S1 obtained by decoding the address signal S16 and the read / write (R / W) signal S17 according to the fetched data and program.
The control information is output from the data bus 15 to the output signal processing unit 11 by 8.

In the output mode in which the CPU 10 processes, as shown in FIG. 2E, the write pulse signal (W / R) from the decoder 14 is generated by the data taken in by the CPU 10.
S19 is output. This write pulse signal (W /
R) The control information signal is output to the output signal processing unit 11 only during the period when S19 is output, and this control information signal is sent from the output signal processing unit 11.

Instead of supplying this address information to the input signal processing section 13, the output port of the CPU 10 can be used to perform the same processing. In this case, the step of operating the output port can be omitted.

[0018]

As is apparent from the above description, in the data input / output processing device of the present invention, the input signal processing means is connected to the bidirectional data bus through the diode, and the address used by the output signal processing means is Since it is connected to another different address and the address line used in the input signal processing means is selected to be substantially zero and the decoding result of the read / write control signal is given to the output signal processing means. , The enabling pulse for fetching the information of the input signal processing means and the conventional buffer are unnecessary. Further, when the same processing is performed using the output port of the central processing unit, the step of operating the output port is omitted. As a result, the circuit scale can be reduced, and the program capacity and the processing time can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data input / output processing device of the present invention.

FIG. 2 is a timing diagram showing processed signals in the configuration of the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional data input / output processing device.

FIG. 4 is a timing chart showing processed signals in the configuration of the conventional example.

[Explanation of symbols]

 10 CPU 11 output signal processing unit 12a, 12n diode 13 input signal processing unit 14 decoder 15 bidirectional data bus S16 address signal S15 data bus signal S17 read / write signal S18 enable pulse signal S19 write pulse signal

Claims (1)

[Claims] 1. An output signal processing means connected to a bidirectional data bus connected to a central processing unit that operates by a program, and a diode connected to the bidirectional data bus and used in the output signal processing means. Input signal processing means connected to another address different from the address,
A data input / output processing device comprising: an address selected so that an address line used by the input signal processing means becomes substantially zero; and a decoding means for giving a decoding result of a read / write control signal to the output signal processing means.