JPH0353310A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To actuate a semiconductor integrated circuit at a high speed despite a low voltage level and the small current consumption by forming a clock driver with plural buffers and tri-state buffers connected in parallel to each other. CONSTITUTION:A buffer 1 and a tri-stete buffer 2 are connected in parallel to each other in a clock driver circuit 27. In a high speed clock action state, an 'H' level is inputted via a terminal 12 and the buffer 2 is turned on. When a clock is inputted from a terminal 11, both buffers 1 and 2 output the clocks to the logic circuits 1 and 2. In a low speed clock action state, an 'L' level is inputted via the terminal 12 and the buffer 2 is turned off. Then only the buffer 1 outputs the clocks to both circuits 1 and 2. As a result conflicting functions being a high speed action and a low voltage/low consumption current action are compatible.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

With the spread and increasing functionality of small portable electronic devices, semiconductor integrated circuits (hereinafter referred to as
At the same time, low-voltage operation and low current consumption are required for LSI (abbreviated as LSI), which can be operated on dry batteries.At the same time, the importance of software processing in the system has increased, and the number of program steps has increased, resulting in faster instruction execution and increased device efficiency. High integration is also required for further miniaturization.

In CMOSLSI, the switching speed of the transistor is largely dependent on the charging/discharging time for the gate capacitance, so as the operating clock becomes faster, the minimum operable power supply voltage increases, and the power supply current increases, excluding analog circuits, etc. Since the charging/discharging current is highly dependent on the gate capacitance, the current consumption tends to increase as the operating clock becomes faster. In order to achieve the contradictory demands of high-speed operation and low-voltage/low-current consumption operation, the operating clock frequency can be switched as necessary (a method especially adopted in single-chip microcontrollers), i.e., internal calculation processing, etc. A high-speed clock is used when high-speed processing is required, and a low-speed clock is used when the key is waiting for human power, enabling low voltage and low current consumption operation. - There is a method to achieve low current consumption operation.

However, as the number of circuit elements increases as LSIs become more highly integrated, the number of gates that input clocks increases, and the wiring length of clock lines also increases, resulting in an increase in the load capacity of the clock driver, which is the sum of gate capacitance and wiring capacitance. Therefore, in order to enable high-speed clock operation, a clock driver that can output more current is required. At the LSI design stage, the clock driver is designed taking into consideration the load capacity and operating speed of the clock driver, so the size of the clock driver is determined so as to satisfy high-speed clock operation. Therefore, this method of switching the clock frequency does not use a clock driver of an optimal size for low-speed clock operation, and a considerable amount of through current flows in the clock driver during low-speed clock operation.

[Problem to be solved by the invention]

As mentioned above, in a semiconductor integrated circuit using a conventional clock driver, when two types of clocks, high speed and low speed, are switched and used, the clock driver is designed to match the high speed clock, so it is optimal for low speed clock operation. Therefore, the current consumed by the clock driver cannot be ignored, and there is a problem that the operating current cannot be reduced even during low-speed clock operation.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has at least a logic circuit and a clock driver that supplies a system clock to the logic circuit, in which the clock driver is connected to a plurality of buffers and a plurality of three-state buffers in parallel. It is connected and constructed. [Example] Buffer 1 and 3-state buffer 2 are connected in parallel to form a clock driver circuit 27. Signal line 5 is a clock line that supplies a clock signal. Clock driver circuit 27 supplies a clock to logic circuit 1 and logic circuit 2 via signal line 5. Input unit 1
1 is a clock input terminal from outside the LSI, input terminal 12
is an on/off control signal input terminal of the 3-state buffer 2.

During high-speed clock operation, an "H" level is input from the terminal 12 to turn on the 3-state buffer 2. terminal 1
When a clock is input from 1, the clock is output from both buffer 1 and 3-state buffer 2, and the clock is supplied to logic circuit 1 and logic circuit 2. The drive capability of the clock driver circuit 27 at this time corresponds to the sum of the drive capabilities of the buffer 1 and the 3-state buffer 2.

During low-speed clock operation, “l L I” is input from terminal ■2.
Input the level and turn 3-state buffer 2 off. When a clock is input from the terminal 11, only the buffer l outputs the clock and supplies the clock to the logic circuit 1 and the logic circuit 2. The driving ability of the clock driver circuit 27 at this time is equal to the driving ability of the buffer 1.

FIG. 2 is a block diagram of a second embodiment of the present invention. Buffer 1 and 3-state buffer 2 are connected in parallel and are connected to clock driver circuit 27. The CPU 25 and the peripheral circuit 26 are connected to a clock driver circuit 27
It operates in synchronization with the clock supplied by. The signal line 5 is a clock line that supplies a clock signal. The oscillation circuit 23 is a crystal oscillation circuit. Terminals 21 and 22 are terminals for connecting a crystal resonator to the outside. The signal line 24 is the CPU 2
This is a signal that becomes the ``LI1'' level when the 5 is in an operation stopped state.

When the CPtJ 25 and the peripheral circuit 26 are in a normal operating state, the three-state buffer 2 is in an on state. Oscillation circuit 2
3 clock outputs to buffer 1 and 3-state buffer 2
The CPU 25 and the peripheral circuit 26 are supplied with the drive signal. The drive capability of the clock driver circuit 27 at this time corresponds to the sum of the drive capabilities of the buffer 1 and the 3-state buffer 2.

When the CPU 25 stops operating, the signal line 24 goes to the "I L I1" level, and the 3-state buffer 2 turns off. At this time, only the buffer 1 drives the clock output of the oscillation circuit 23. , is supplied to the CPU 25 and the peripheral circuit 26. At this time, the clock driver circuit 2
The drive capacity of buffer 7 is equal to the drive capacity of buffer 1. Although the above explanation uses a crystal oscillation circuit, other oscillation circuits can be applied in the same way.

As explained above, the semiconductor integrated circuit of this example has a CP
This has the effect of suppressing the through current in the clock driver circuit 27 by reducing the drive capability of the clock driver circuit 27 when the U25 is in a non-operational state.

〔Effect of the invention〕

As explained above, according to the present invention, in a semiconductor integrated circuit that switches between a high-speed clock and a low-speed clock, the high-speed clock By using a sufficiently large clock driver for operation and using a small clock driver for low-speed clock operation, the current consumed by the clock driver can be reduced, making it possible to achieve the contradictory functions of high-speed operation and low-voltage/low-current consumption operation. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a block diagram of a second embodiment of the present invention. 1...Buffer, 2...3 state buffer, 3.
...Logic circuits 1, 4...Logic circuits 2, 5...Clock supply line, 11...Clock input terminal゜, 12...
・3-state buffer control signal input terminal, 21.22
...Crystal resonator connection terminal, 23...Crystal oscillation circuit,
24... Operation stop state signal, 25... CPU, 26
... Peripheral circuit, 27... Clock driver circuit.

Claims (1)

[Claims] In a semiconductor integrated circuit that has at least a logic circuit and a clock driver that supplies a system clock to the logic circuit, the clock driver is connected to a plurality of buffers and a plurality of control gates that are controlled based on arbitrary signals. A semiconductor integrated circuit comprising three state buffers connected in parallel.