JPH05298089A - Register - Google Patents

Abstract

PURPOSE:To provide the register which reduces the program size and effectively uses a data storage area. CONSTITUTION:The operation of a circuit corresponding to each bit of a register connected to a central processing unit 1 is controlled in accordance with bit data of the register 9. This register 9 designated by one address is characterized by providing a first area 12 in and from which data can be written and read out and second areas 4 and 7 which operate circuits by write operation of '0' or '1' data and send '1' or '0' data, which do not operate the circuits, to the central processing unit 1 at the time of access of the central processing unit 1 to the first area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register connected to, for example, a central processing unit.

[0002]

2. Description of the Related Art Conventionally, as a type of register combined with a central processing unit, for example, if "1" is written in a certain bit of the register, "1" can be read, that is, the value written in the register can be read. Of the
On the contrary, there is a type in which the written value cannot be read, that is, the operation of the device at the next stage connected to the register is controlled by the operation of writing the value to the register. On the other hand, one of the instructions processed by the central processing unit is to read the value written in a register, set or reset only the necessary bits, and write the set or reset data in the register in one step. There is a bit operation instruction which is a function executed by the instruction of.

As a method of controlling each bit data of the register when the operation of a single function circuit that performs a certain single function is controlled by each bit data in the register, the written value described above can be read out. In the case of a register of a non-type, as shown in FIG. 4, only the bit data of the register corresponding to the above-mentioned single function circuit to be activated should be a value that should be activated, and other bit data should be an immediate value that is not activated. There is a method of reading into the accumulator and writing the value from the accumulator to the above register. Further, in the case of the type of register in which the written value can be read, the above bit manipulation instruction may be used.

[0004]

However, as mentioned above,
Assuming that the bit whose written value cannot be read and the bit whose written value can be read coexist in the same register, that is, in the same address, the bit whose written value cannot be read is shown in FIG. As described above, when the written value is changed by the bit manipulation instruction, the original value must be rewritten. In this way, if bits with different functions are assigned to the same address, there is a problem that an extra command description sentence of rewriting the value is required, the program size becomes large, and the program efficiency is not good. There is also a problem that the calculation time is delayed due to the increase of Therefore, conventionally, bits having different functions as described above have not been allocated to the same address, and a 1-byte area occupies even the stored data consisting of several bits, so that the data storage area in the data storage device is efficient. There was also a problem that it was not used for a long time. The present invention has been made to solve such a problem, and provides a register capable of reducing the program size, shortening the calculation time, and effectively utilizing the data storage area. The purpose is to

[0005]

According to the present invention, a register for controlling the operation of a circuit corresponding to each bit of a register connected to a central processing unit is designated by a single address. The register is configured to operate the circuit by a first area in which data can be written and the written data can be read, and the circuit can be operated by a write operation of 0 or 1 data. It is characterized in that it is provided with a second area for sending 1 or 0 data which does not operate the circuit to the central processing unit when accessing.

In the second area, when a write signal is supplied from the central processing unit, data to be sent from the central processing unit is sent to a circuit whose operation is controlled by the first data. It is possible to provide a sending means and a data second sending means for sending the data of 1 or 0 which does not operate the circuit to the central processing unit by receiving the read signal from the central processing unit. The first region can be composed of a latch circuit.

[0007]

With this configuration, when the register which is the data storage location at a certain address is designated and the bit operation instruction is executed, when the central processing unit accesses the first area, the second area becomes Since the data that does not operate the circuit that operates by the data write operation to the second area is sent to the central processing unit, it is not necessary to rewrite the value in which the circuit corresponding to the second area does not operate unlike the conventional case. , The program size is reduced and the processing time is shortened.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the register of the present invention will be described below with reference to FIG. The register 9 shown in FIG.
It is one of a plurality of registers and has one address value attached, and consists of 3 bits.
The bit has a configuration capable of only writing data from the central processing unit 1, and the remaining 1 bit has a configuration capable of reading and writing data. The number of constituent bits of the register 9 and the details of the above description are not limited to those described above. The register 9 may be provided in the same integrated circuit as the central processing unit 1 or may be provided separately.

One signal line of the data bus connected to the central processing unit 1 is connected to the input side of the tri-state buffer 4a which is one of the first bit components of the register 9. The tri-state buffer 4a is a selection signal transmitted by the address decoder 2 which demodulates an inverted signal of the write control signal transmitted from the central processing unit 1 (hereinafter referred to as an inverted write signal) and an address signal for designating a register. The output side of the AND circuit 10 that performs a negative logical product operation of the inverted signal of the signal (hereinafter, referred to as the inverted selection signal) is connected to the disable terminal, and a negative level output signal is supplied from the AND circuit 10 The data obtained by inverting the output signal of the arithmetic processing unit 1 is set to the transmission state. The output side of such a tri-state buffer 4a is connected to a single-function circuit 3 which functions with the signal "1" sent from the central processing unit 1.

The output side of the tri-state buffer 4b, which is one of the first bit constituent parts of the register 9, is connected to the input side of the tri-state buffer 4a. The tri-state buffer 4b has an input side grounded, and an inverted signal of a read control signal (hereinafter referred to as an inverted read signal) sent from the central processing unit 1 and the address decoder 2 described above.
AN which performs a negative logical AND operation of the inverted selection signals transmitted by the
The output side of the D circuit 11 is connected to the disable terminal,
When the negative level output signal is supplied from the AND circuit 11, the negative level data is sent to the central processing unit 1. Incidentally, the above-mentioned tri-state buffer 4a
And 4b form the first bit of the register 9.

Similar to the first bit of the register 9 described above, the second bit of the register 9 is similarly configured. That is, one signal line of the central processing unit 1 is connected to the input side of the tri-state buffer 7a which is one of the second bit constituent parts of the register 9. The output side of the AND circuit 10 is connected to a disable terminal of the tri-state buffer 7a, and a negative level output signal is supplied from the AND circuit 10 to put the output signal of the central processing unit 1 into a data transmission state. .. The output side of such a tri-state buffer 7a is connected to a single function circuit 8 which functions with the output signal of "0" of the central processing unit 1.

The input side of the tri-state buffer 7a is connected to the output side of the tri-state buffer 7b which is one of the second bit constituent parts of the register 9. The tri-state buffer 7b has an input side connected to a power supply of a predetermined potential, an output side of the AND circuit 11 connected to a disable terminal, and a negative level output signal supplied from the AND circuit 11 to thereby provide a central processing unit. A positive level data is sent to 1. The tristate buffers 7a and 7b described above form the second bit of the register 9. As described above, the 1st and 2nd bits of the register 9 constitute bits that can be written only.

The third bit of the register 9 is a bit for reading and writing data. One signal line of the central processing unit 1 is connected to the input terminal of the latch circuit 12 which constitutes the second bit of the register 9. The latch circuit 12 is
The output side of the AND circuit 10 is connected to the clock terminal of the latch circuit 12, and a negative level output signal is supplied from the AND circuit 10 to take in the output signal of the central processing unit 1. The output side of the latch circuit 12 is connected to the circuit of the next stage, and the output side of the AND circuit 11 is connected to the input side of the tristate buffer 12a connected to the disable terminal. The output side is connected to the input side of the latch circuit 12.

Therefore, the latch circuit 12 is the AND circuit 10
Is supplied with the inverted write signal to take in the data transmitted by the central processing unit 1, while the AND circuit 11 is supplied with the inverted read signal to transfer the data stored in the latch circuit 12 via the tri-state buffer 12a. And sends it to the central processing unit 1.

The operation of the register thus constructed will be described below. The register is designated by the address signal transmitted from the central processing unit 1. Now, assume that the register 9 shown in FIG. 1 is designated. Next, when the central processing unit 1 executes the bit operation instruction for writing the data of "1" into the buffer 4 which is the first bit of the register 9, the central processing unit 1 first performs the read operation, so the AND circuit 11 An inverted read signal is transmitted from the tristate buffer 4b
Becomes an operating state, and the buffer 4 sends data of "0" to the central processing unit 1. Therefore, the data “0” is read from the buffer 4.

Next, the central processing unit 1 includes the buffer 4
By performing the write operation to the AND circuit 10, the inverted write signal is sent from the AND circuit 10 and the tri-state buffer 4a becomes the operating state, so that the data of "1" is sent from the central processing unit 1 to the buffer 4. Then, the inverted "0" data is written in the. Therefore, the data of "0" is supplied from the buffer 4 to the clear terminal of the single function circuit 3, and the single function circuit 3 is cleared.

When the central processing unit 1 executes a bit manipulation instruction for manipulating bits other than the buffer 4 of the register 9, the central processing unit 1 outputs data of "0" from the buffer 4 as described above. After reading, the data of “0” is sent to the buffer 4. Therefore, the data of "1" that is the inverted "0" is written in the buffer 4, and the buffer 4
Since the data of "1" is sent from the single function circuit 3 from
The single function circuit 3 is not cleared.

Similarly, the central processing unit 1 controls the register 9
When a bit operation instruction for writing "0" data to the second-bit buffer 7 is executed, the central processing unit 1 first performs a read operation. Therefore, an inverted read signal is sent from the AND circuit 11 and the tristate buffer 7b is output. Becomes an operating state, and the buffer 7 sends the data of "1" to the central processing unit 1. Therefore, the data “1” is read from the buffer 7. Next, the central processing unit 1
By performing the write operation to the buffer 7, the inverted write signal is sent from the AND circuit 10 to activate the tri-state buffer 7a, the data of "0" is sent to the buffer 7, and the data of "0" is sent to the buffer 7. Data is written. Therefore, the data of "0" is sent from the buffer 7 to the clear terminal of the circuit 8 having a single function. Therefore, the single function circuit 8 is cleared.

When the central processing unit 1 executes a bit manipulation instruction for manipulating a bit other than the buffer 7 of the register 9, the central processing unit 1 sends data of "1" from the buffer 7 as described above. After reading, the data of "1" is written to the buffer 7 again, so that the data of "1" is sent from the buffer 7 to the single function circuit 8 and the single function circuit 8 is not cleared.

On the other hand, as described above, the latch circuit 12 receives the data sent from the central processing unit 1 by being supplied with the inverted write signal from the AND circuit 10, and the latch circuit 12 receives the inverted read signal from the AND circuit 11. By being supplied, the data stored in the latch circuit 12 is sent to the central processing unit 1 via the tri-state buffer 12a. The operations described above are shown collectively in FIG.

FIG. 2 shows how the registers change when the bit manipulation instructions are continuously executed.

As described above, in the central processing unit having the bit operation instruction, the bit which has a meaning only when only a specific value is written and the bit which has a meaning for both "0" and "1" data are provided. Even if they are placed in the register of the same address, the bit operation instruction affects the data specified by the bit operation instruction other than the data readable and writable bits, that is, the data in the bit that can only be written. However, it is possible to write data to the register with a one-step instruction. Therefore, the program size can be reduced, and the program execution processing time can be shortened. Further, the program size can be reduced to efficiently use the data storage area.

As a concrete example, when the conventional registers shown in FIGS. 4 and 5 are used, the number of program bytes requires 4 bytes, and the program processing time requires 5 machine cycles and 10 machine cycles. However, when the register of this embodiment shown in FIG. 3 is used, the number of program bytes is 2 bytes, and the processing time is 5 machine cycles.

[0024]

As described above in detail, according to the present invention, when a register which is a data storage location at an address is designated and a bit operation instruction is executed, the central processing unit accesses the first area. Since the second area sends data to the central processing unit that does not operate the circuit that operates by writing data to the second area, the value that does not operate the circuit corresponding to the second area as in the conventional case. Therefore, it is possible to reduce the program size and the processing time without rewriting.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a register of the present invention.

FIG. 2 is a diagram showing how registers are changed when bit manipulation instructions are continuously executed in the register of the present invention.

FIG. 3 is a flowchart showing an operation of the register of the present invention.

FIG. 4 is a flowchart showing an operation of a conventional register.

FIG. 5 is a flowchart showing an operation of a conventional register.

[Explanation of symbols]

1 ... Central processing unit, 3 ... Single function circuit, 4 ... Buffer, 7 ... Buffer, 8 ... Single function circuit, 9 ... Register, 10 and 11 ... AND circuit.

Claims (3)

[Claims] 1. In a register for controlling operation of a circuit corresponding to each bit of the register according to each bit data of the register connected to the central processing unit, writing of data to a register designated by one address. And a first area from which the written data can be read, and the circuit is operated by a write operation of 0 or 1 data, and the circuit is operated when the central processing unit accesses the first area. And a second area for sending 1 or 0 data which is not operated to the central processing unit. 2. The first area is a data area for sending data sent from the central processing unit to a circuit whose operation is controlled by the sending data when a write signal is supplied from the central processing unit. 2. The data transmitting means according to claim 1, further comprising a transmitting means and a data second transmitting means for transmitting data of 1 or 0 which does not operate the circuit to the central processing unit when a read signal is supplied from the central processing unit. register. 3. The register according to claim 1, wherein the first region is composed of a latch circuit.