KR100257078B1 - Interface device of core and peripheral circuit - Google Patents

Abstract

PURPOSE: An interface device between an internal and a peripheral circuit is provided to simply and variously control the peripheral circuit by adding a bit manipulation function. CONSTITUTION: An interface device between an internal circuit(21) and a peripheral circuit(22) transmits an address bus, an enable signal, the first and the second control signal to the peripheral circuit(22) from the internal circuit(21). The internal circuit(21) and the peripheral circuit(22) transmit and receive data through a data bus. The peripheral circuit(22) transmits an interrupt signal to the internal circuit(21).

Description

Interface device of internal circuit and peripheral circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface device, and more particularly, to an interface device of a suitable internal circuit and a peripheral circuit that can easily and variously control a peripheral circuit including a bit adjustment function.

In general, an interface device between an internal circuit and a peripheral circuit usually has a function in which an internal circuit writes or reads a value in a register of a peripheral circuit, and an interrupt that the peripheral circuit sends to the internal circuit ( Interrupt).

Hereinafter, referring to the accompanying drawings, a conventional interface device between an internal circuit and a peripheral circuit will be described.

1 is a block diagram illustrating an interface device between a conventional internal circuit and a peripheral circuit.

As shown in FIG. 1, the interface device of the internal circuit 11 and the peripheral circuit 12 includes an address bus, a data bus, an enable, a read / write. And an interrupt signal.

2 is a block diagram of a peripheral circuit for satisfying the interface bus of FIG.

As shown in Fig. 2, an address decoder 13 for interpreting an address through an address bus and outputting a plurality of register select signals Reg1_Select, Reg2_Select, ..., RegN_Select, and the address decoder 13, A plurality of registers 14 for receiving and outputting a register select signal, a data bus, enable, and a read / write signal, and a peripheral core logic unit for outputting an interrupt signal according to the states of the registers 14; It consists of 15 pieces.

3 is a circuit diagram illustrating one register in the peripheral circuit of FIG. 2.

As shown in FIG. 3, the D-flip flop 16 storing data through the data bus and the read / write signal are inverted by the inverter 17, the register select signal, and the enable signal are logically operated. A first AND gate 18 for enabling the D-flip flop 16, a second AND gate 19 for receiving and enabling logic of an enable signal, a read / write signal, and a register select signal, and the second It is composed of a tri-state buffer 20 which is enabled by the AND gate 19 and outputs the data value of the D-flip flop 16 to the internal circuit 11.

Referring to the operation of the interface device of the conventional internal circuit and the peripheral circuit configured as described above are as follows.

As shown in FIG. 1, the internal circuit 11 provides an address, enable, read / write signal to the peripheral circuit 12, receives an interrupt signal, and gives or receives data.

First, the internal circuit 11 outputs an address corresponding to the register 14 to be read or written to the peripheral circuit 12 through the address bus, and outputs an enable signal and a read / write signal.

In this case, when the read / write signal corresponds to a light, data is also sent to the peripheral circuit 12 through the data bus.

The address decoder 13 of the peripheral circuit 12 then analyzes which register 14 the internal circuit 11 intends to address and sends a register select signal to the corresponding register 14.

Subsequently, when the read / write signal sent from the internal circuit 11 is a read, the register 14 receiving the register select signal has the D-flip flop 16 enabled as shown in FIG. 14 is stored.

When the read / write signal is a write, the contents of the register 14 stored by the tri-state buffer 20 are enabled and transferred to the internal circuit 11 through the data bus.

Subsequently, the peripheral core logic unit 15 varies considerably depending on the characteristics of the peripheral circuit 12, but when certain conditions are satisfied, the internal circuit 11 processes the work by sending an interrupt signal to the internal circuit 11.

However, the above-described conventional interface device between the internal circuit and the peripheral circuit has the following problems.

That is, the register of the peripheral circuit is composed of several bits, and the operation of the peripheral circuit varies depending on the value of each bit. Therefore, in the peripheral circuit, if the internal circuit wants to change only a specific bit of the register of the peripheral circuit, it reads the contents of the register, operates on the specific bit, changes the value, and writes back to the register of the peripheral circuit. Was done.

The present invention has been made to solve the above problems, by adding a bit manipulation function (Bit Manipulation) to the interface device of the internal circuit and the peripheral circuit to perform a simple and various control of the peripheral circuit (Control) The purpose is to provide.

1 is a block diagram showing an interface device between a conventional internal circuit and a peripheral circuit;

2 is a block diagram of a peripheral circuit for satisfying the interface bus of FIG.

3 is a circuit diagram illustrating one register in the peripheral circuit of FIG. 2.

4 is a block diagram showing an interface device between an internal circuit and a peripheral circuit according to the present invention.

5 is a block diagram illustrating an interior of a peripheral circuit of FIG. 4.

FIG. 6 is a circuit diagram illustrating one register in the peripheral circuit of FIG. 5. FIG.

7 is an internal circuit diagram of a one bit cell used in the register of FIG.

Explanation of symbols for the main parts of the drawings

21: internal circuit 22: peripheral circuit

23: address decoder 24: register

25: peripheral core logic section 26: 1-bit cell

28: first AND gate 29: second AND gate

30: tri-state buffer 32: third AND gate

35: fourth AND gate 36: latch portion

27,31,32,34: Inverter

The interface device of the internal circuit and the peripheral circuit according to the present invention for achieving the above object, in the interface device of the internal circuit and the peripheral circuit, the address bus, enable, the first, the second control signal in the internal circuit It is characterized in that it is configured to send to the peripheral circuit, the internal circuit and the peripheral circuit send data to each other through the data bus, and send the interrupt signal to the internal circuit.

Hereinafter, the interface device of the internal circuit and the peripheral circuit according to the present invention with reference to the accompanying drawings in detail as follows.

4 is a block diagram illustrating an interface device between an internal circuit and a peripheral circuit according to the present invention.

As shown in FIG. 4, the interface device of the internal circuit 21 and the peripheral circuit 22 sends an address bus, enable, first and second control signals from the internal circuit 21 to the peripheral circuit 22. The internal circuit 21 and the peripheral circuit 22 exchange data with each other through the data bus, and the peripheral circuit 22 sends the interrupt signal to the internal circuit 21.

FIG. 5 is a block diagram illustrating the interior of the peripheral circuit of FIG. 4.

As shown in FIG. 5, an address decoder 23 that interprets an address through an address bus and outputs a plurality of register select signals Reg1_Select,..., RegN_Select and bit select signals Bit1_Select, ..., BitN_Select. And a plurality of registers 24 for receiving and outputting the register select signal and the bit select signal of the address decoder 23, the data bus, enable, the first and second control signals, and the state of the register 24. Therefore, it is composed of a peripheral core logic (Peripheral Core Logic) unit 25 for outputting an interrupt signal.

FIG. 6 is a circuit diagram illustrating one register in the peripheral circuit of FIG. 5.

As shown in FIG. 6, the plurality of 1-bit cells 26 that receive the first and second control signals and store n-bit data through the data bus and the second control signals are inverted by the inverter 27. A first AND gate 28 for receiving each of the 1-bit cells 26 by performing a logic operation on the received signal, the register select signal, the enable signal, and the first control signal, and the enable signal, the register select signal, and the first control signal. The second AND gate 29 which receives the first and second control signals and performs a logical operation, and the second AND gate 29 enable the data value of each one-bit cell 26 to the internal circuit 21. It consists of a Tri-State Buffer (30) which outputs.

7 is an internal circuit diagram of one bit cell used in the register of FIG.

As shown in FIG. 7, the bit AND signal and the inverter 31 receive the inverted signal of the first control signal, the second control signal and the enable signal, and perform a logic operation to output a set signal. The gate 32 and the bit select signal and the two inverters 32 and 33 receive the inverted and enable signals of the first and second control signals and perform logic operations to output a reset signal. And a latch portion 36 for outputting data by the set signal of the third AND gate 32 and the reset signal of the fourth AND gate 35.

Referring to the operation of the interface device of the internal circuit and the peripheral circuit according to the present invention configured as described above are as follows.

First, the meanings of the first control signal and the second control signal are as follows.

The first control signal and the second control signal

"0,0" → bit reset (make the corresponding bit "0"),

"0,1" → bit set (makes the corresponding bit "1"),

"1,0" → register read (reads the value of the corresponding register through the data bus)

"1,1" → write register (writes the value of the data bus to the register)

Of the four cases described above, "1,0" and "1,1" are the same as those of the conventional read / write control.

That is, in the case of "1,0" and "1,1", since the first control signal is "1", the first and second AND gates 28 and 29 are enabled in FIG. 6, and the second control signal is "1". 1 ", one bit cells of register 24 are enabled so that the signal of the data bus is stored in all one bit cells 26 of register 24.

In addition, when the second control signal is "0", the enable signal of the one-bit cell 26 of the register 24 is turned off, and the enable signal of the tri-state buffer 30 (the second AND gate). The contents of the ON register 24 are transferred to the internal circuit 21 via the data bus.

On the other hand, when the first control signal is "0" and the second control signal is "0", the fourth AND gate 35 of the corresponding bit cell is enabled so that the content of the bit cell 26 is set to "0". Make.

Next, when the first control signal is "0" and the second control signal is "1", the third AND gate 28 of the corresponding bit cell 26 is enabled to change the contents of the bit cell 26. Is made of 1 ".

In the interface device of the present invention, each register 24 and each bit cell 26 have the same address. This is because the first and second control signals distinguish each bit from the register.

As described above, in the interface device of the internal circuit and the peripheral circuit according to the present invention, when the internal circuit is intended to modify one bit of a register in the peripheral circuit, only one bit can be accessed and processed at high speed, thereby reducing power consumption. It works.

Claims (4)

In the interface device of the internal circuit and the peripheral circuit, Sending the address bus, enable, first and second control signals to the peripheral circuit from the internal circuit, the internal circuit and the peripheral circuit exchange data with each other through the data bus, and interrupt signal to send the peripheral circuit to the internal circuit Interface device of the internal circuit and the peripheral circuit, characterized in that configured. The method of claim 1, wherein the peripheral circuit An address decoder for interpreting an address through an address bus of the internal circuit and outputting a plurality of register select signals and bit select signals; A plurality of registers for receiving and outputting a register select signal and a data bus, enable, first and second control signals of the address decoder; And an peripheral core logic unit configured to output an interrupt signal to the internal circuit according to the state of the register. The method of claim 2, wherein the register is A plurality of 1-bit cells receiving the first and second control signals and storing n-bit data through a data bus; A first AND gate configured to receive the inverted signal of the second control signal, the register select signal, the enable signal, and the first control signal to perform a logical operation to enable each one-bit cell; A second AND gate configured to receive the enable signal, the register select signal, and the first and second control signals and perform a logical operation; And a tree-state buffer enabled by the second AND gate and outputting data values of each one-bit cell to an internal circuit. The method of claim 3, wherein the 1-bit cell is A third AND gate configured to receive the bit select signal of the address decoder, the inverted signal of the first control signal, the second control signal, and the enable signal, and perform a logic operation to output a set signal; A fourth AND gate configured to receive the bit select signal of the address decoder, the inverted signal of the first and second control signals, and the enable signal, and perform a logic operation to output a reset signal; And a latch unit configured to output data according to the set signal of the third AND gate and the reset signal of the fourth AND gate.

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