JPS63263526A - Information processing system - Google Patents

Abstract

PURPOSE:To improve the program efficiency by using at least one register of a register group as the register which can be accessed with a variable bit width, which is not restricted by the word length, as a unit. CONSTITUTION:A variable length register 3 having a longer bit length is provided besides a register group 2 which can be used in the conventional manner, and an instruction group which accesses the variable length register 3 is set. This instruction group includes an instruction LOADV which transfers data from the variable length register 3 to a conventional register, an instruction STOREV which transfers data from a conventional register to the variable length register 3, an instruction MOVEV which transfers data between a memory and the variable length register 3, instructions ADDV, SUBV, ANDV, and ORV which perform the arithmetic processing between the variable length register 3 and the conventional register group 2, etc. Since the variable length register 3 and the instruction group which accesses this register are provided, the change of software which uses conventional register group 2 and instruction group is not necessary and the compatibility with a conventional computer is kept.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a computer system equipped with a variable-length register and an instruction for performing bit-by-bit processing on the register. The present invention relates to a computer system suitable for calculating bit-number data.

[Conventional technology]

Conventionally, computer architectures capable of manipulating data in bit units have been discussed in the MC68020 User's Manual (1986) and the like. Such an architecture can perform arbitrary bit operations on data with a bit length of less than a word unit, but data with a bit length of more than a word unit, such as data of 100 bits or 200 pits, can be manipulated as is. However, the operation is performed by dividing it into bytes or words, which leads to a decrease in efficiency.

[Problem that the invention seeks to solve]

The above conventional technology assumes that the data to be operated on is operated on a register with a fixed length. Therefore, the LOAD instruction, etc. that moves data from memory to a register, requires the entire length of the register or half of it in bits. This operation is like extracting long data from memory. However, if the data to be handled is long, such as 100 or 200 bits, no consideration was given to the fact that it would not be stored in fixed-length registers, resulting in a problem with lower execution efficiency. .

The purpose of the present invention is to provide a variable-length register for each bit while maintaining compatibility with conventional software without changing the basic part of the conventional computer architecture, and to use a group of instructions for the register to control the number of small bits. To provide a variable-length register computer that can use data with a large number of bits for calculations without impairing execution efficiency.

[Means for solving problems]

In addition to the conventional registers that can be used, the above purpose is to
A variable length register with a large bit length is provided.

This is achieved by setting a group of instructions that access the variable length register. It is assumed that the length of the variable length register is the length of a plurality of conventional registers, and each bit position is addressable. A new set of instructions for accessing the variable-length register is provided in addition to the conventional set of instructions. Such instructions include LOAD, which moves data from variable-length registers to conventional registers.
V, 5TOREV which performs the opposite operation, MOVEV which moves data between the memory and the variable length register, A which performs arithmetic processing between the variable length register and the conventional register.
Includes instructions such as DDV, 5UBV, ANDV, ORV.

By newly creating the variable-length register and the instruction group that accesses it in addition to the conventional register group and instruction group, software that uses the conventional register group and instruction group does not need to be changed and is compatible with conventional computers. Compatibility can be maintained. Note that the instruction to access the variable register will be referred to as an RV instruction hereinafter.

[Effect]

All RV instructions access variable-length registers, and one of them, the LOADV instruction, uses the conventional register as the first operand, the bit position on the variable-length register as the second operand, and the length of the data as the third operand. specify. When the instruction is executed, it operates to move data from the bit position pointed to by the second operand of the variable-length register to the register pointed to by the first operand by the number of bits of the length specified by the third operand. Thereby, if the specified number of bits is longer than the register of the first operand, the overflow portion is moved to the register following the register pointed to by the first operand.

If that register overflows, it will be moved to the next register, and so on, and if the last register overflows, it will be moved to the first register. Malfunctions are unlikely to occur.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the basic configuration of an embodiment of the present invention, in which 1 is an arithmetic unit, 2 is a register group, 3 is a variable length register, and 4 is a data register for temporarily saving arithmetic results. , 5, 6.7 are gate switches for controlling input/output to the arithmetic unit, and 8 is a main storage device. The second register group has 0, 1, 2, . ..., and the 8 main memories are numbered 0, 1, 2, . ...
Addressing is done in byte units. Previously, input/output to the arithmetic unit was through only 2 register groups, but now 1
In the present invention, the three variable-length registers are also subject to input/output to the arithmetic unit, and which one is the input source.

Alternatively, gate switches 5 and 6.7 control whether the light is selected as output light. The gate switch.

Conventionally, one register was selected from two register groups, but in this embodiment, three variable-length registers are also selected.

FIG. 2 is a diagram showing the RV all command format, and 9 is an example of the RV all command. In this embodiment, the total RV instruction length is 32 bits, of which 0 to 7 bits are LOADV, 5TO
Instruction code that identifies the type of instruction such as RHV, 8 to 11
bit is the length of the data, expressed as below), 12 to 1
The 5 bits are the register address (hereinafter referred to as R) that is the first operand.
(represented as 1).

The 16th to 19th bits are the register address (hereinafter referred to as BS) that points to the bit position on the variable length register that becomes the second operand, and the 20th to 31st bits are the displacement value from 82 to access the second operand. (hereinafter D2
), R1 refers to a register that is one of the 16 registers, and the bit position on the variable-length register where the data begins is specified by the value of the contents of the register pointed to by B2 plus the displacement of B2. Ru. In the case of the LOADV instruction, it means to transfer data from the bit position on the variable length register indicated by the content of B2+D2 to the register indicated by R1 by the number of bits indicated by L.
5TOREV is the contents of B2 on the variable length register +D
This means that data for L pits is transferred from the register indicated by Ri to the bit position No. 2. Also,
Taking ADDV as an example, the operation instruction adds the contents of the register indicated by R1 and the value indicated by the L bit from the bit position on the variable length register of B2 contents + Da, and stores the result in R1. Performs the process of storing.

The above device is constructed by configuring at least the arithmetic unit 1 and the register group 2 on the same semiconductor chip)
It is possible to provide chips with excellent productivity, mass productivity, and compatibility with conventional systems.

Next, the flow of processing according to the present invention will be explained using the flowchart shown in FIG. The above instruction word is “LOADV Ri
, D, Rj, L'', Ri represents the i-th conventional register, which is the first operand, and Rj and D represent the i-th conventional register, which is the first operand.
In the operand, the bit position on the variable length register is represented by the sum of the values of D of the contents of the conventional register Rj, and L is the number of bits to be transferred. Also, the pit length of the conventional register is C
Suppose we set temporary variables n and k. As shown in Figure 3, the process flow is as follows: First, add the contents of Rj and D to find the bit position in the variable-length register, then set n to 0. What register is the first operand? 0 Next, transfer L bits from bit position gn on the variable length register to the Rk register. 0 Next, check whether the transfer bit length is greater than the register pit length C, and if not, end the process. do. If L is larger than C, all data has not been transferred, so the value obtained by subtracting C from L is set as new L, the value obtained by adding C to n is set as new n, and
The transfer process is repeated using the value obtained by adding 1 to k as a new k, and when L becomes smaller than or equal to C, the process ends.

〔Effect of the invention〕

According to the present invention, the manipulation of data with a large number of bits or a small number of bits, which was extremely difficult in the past, is now possible using a basic part of the conventional architecture by setting variable-length registers and a group of instructions to access them. This can be easily done without changing the data and while maintaining compatibility with conventional software. Numerical operations require fewer instructions, which has the effect of increasing program efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the format of the RV instruction of the present invention, and FIG. 3 is a flowchart showing the flow of processing in the LOADV instruction. 1... Arithmetic unit, 2... Register group, 3...
Variable length register, 4...Data register, 5, 6.7
...Gate switch, 8...Main storage device, 9...
RV command format. Y1 diagram

Claims (1)

[Claims] 1. In an information processing device having a main memory device, a register group, and an arithmetic means, at least one register in the register group is set in units of a variable bit width that is not restricted by word length. An information processing method characterized by using accessible registers. 2. The information processing system according to claim 1, characterized in that the register group and the calculation means are housed in the same semiconductor chip.