JPS6129940A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To attain ease of pipeline control by executing a read of converting constant depending on an operation data with a fixed number at high speed without branching of a microinstruction so as to save the total processing cycle. CONSTITUTION:A constant memory address generating circuit 12 consists of a gate 14, AND gates 15, 16, and an OR gate 17. An address of a constant memory 8 is given by a K-field output 8-bit of a normal control memory CS7. A code output S of an operand 1-input register 1 is replaced into the least significant bit of the K-field 8-bit of a CS read register CSR5 depending on the value of an address change flag bit 3a of the constant memory output register 3. When the address change flag 3a is logical 0 and the K-field output of the CSR5 is K0- K7, the address of the constant memory 8 is similarly K0-K7. When the flag 3a is logical 1, the address is modified as K0-K6S by the code output S of the operand 1-input register 1.

Description

[Detailed description of the invention] Technical field to which the invention belongs The present invention relates to an arithmetic device.

This relates to a method of supplying calculation constants that depend on calculation data.

Description of prior art Conventional data conversion instructions such as binary to decimal conversion.

Binary data is expressed in two's complement, whereas decimal data is expressed in absolute value, so the microinstruction checks the sign of the binary data and branches, and if it is positive, reads the conversion constant λ,
In the case of jj, the first method is to read the two's complement value Y of λ and perform the calculation, or if the binary data is negative, the two's complement value is fixedly calculated by (X-1). A second method has been used in which calculation is performed by reading out the conversion constant λ.

However, the first method has the disadvantage that processing for determining whether binary data is positive or negative is added (fixed), which reduces arithmetic performance and increases the number of microinstruction steps. However, the arithmetic performance deteriorates when the binary data is negative, the number of T is variable depending on the data, and pipeline control is not suitable.

The configuration of a conventional arithmetic unit of this type is shown in FIG. 1, and the supply time chart of a conversion constant is shown in FIG. 2, which will be described below.

In Figure 1, 1 is an operand 1 manual register that stores the operation data from the 8VR memory, and 2 is an operand 2 register.
Manual register, 3 is constant memory output register, 4 is calculation result register, 5 is C8 which receives the output of control memory C8
A read register (hereinafter referred to as CAR), 6 is a CS address register that provides a read address to control memory C8, 7 is a sequence control field SQN of C8, an arithmetic control field /l/)'' CNT, a constant field and a primary address field. Control memory (called C8) consisting of 4 fields of NA, 8 is a constant memory that stores constants used in conversion instructions, 9 is the output of CS address register 6, and the sign output of operand l input register 1 is 8QN
The branch circuits modified by the field instructions are shown respectively.

(First step) The start address of the conversion instruction is set in the CS address register (hereinafter referred to as C8A) 6 upon activation of the instruction.

(Second step) Next execution address A1 is set to C8A6, and C6H
5, the contents of the first address A1, that is, the operand 1 read instruction (AI) is read out.

(Third step) Execution address As is set to C8A6 one after another, and C8R
5, the contents of the next execution address A2, that is, the operand 1 hold instruction (A2) is read out. In response to the operand 1 read instruction (A1), the operand 1 input register 1 receives the operation data D to be converted from the SVl'L memory 10.
is set.

(Fourth step) Calculated data D is sent to the output of C8A6 by E branch circuit 9.
The content of the output A1', that is, the address designation (AI') to the operand 1 hold and constant memory is read out to C8R5 (execution of decision branch). Operand 1 input register 1 is held by operand 1 hold instruction (A).

(Fifth step) Operand l input register 1 is held by operand 1 hold instruction and constant memory address specification (AI'), and conversion constant λ or r corresponding to the sign of operation data D is stored in constant memory output register 3. Determine.

As explained above, the conventional apparatus shown in FIG. 1 requires 3T to determine the conversion constant, has the drawbacks of slow start-up of calculation execution, and increased microphone program capacity.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks inherent in the prior art.Therefore, it is an object of the present invention to provide a memory means for storing constants and address changes necessary for the execution of arithmetic operations. According to the instruction, conversion constants that depend on operation data can be read out at high speed without decision branching of microinstructions.

Structure of the Invention In order to achieve the above object, an arithmetic device according to the present invention includes means for storing arithmetic data, memory means for storing constants and address change flags necessary for execution of an arithmetic operation, and a memory means for storing the arithmetic data. and means for modifying the address of the memory means by the value of the storage means and the value of the address change flag of the memory means.

DETAILED DESCRIPTION OF THE INVENTION Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention;
The figure is a block diagram showing an example of a detailed configuration of the constant memory address generation circuit and its peripheral circuits shown in FIG. 3, and FIG. 5 is a diagram showing an example of an operation time chart thereof.

In FIG. 3, reference number 1 is an operand 1 input register that stores operation data from the SVR memory, 2 is an operand 2 manual register, 3 is a constant memory output register,
4 is an operation result register, 5 is a C8 read register (hereinafter referred to as CAR) that receives the output of the control memory CB, 6 is a CS address register that provides a read address to C8, 7 is a sequence control field 8QN of cs, an operation control field CNT, a control memory (consisting of 4 fields including a constant field and a 5th address field NA)
(referred to as C8).

Constant memory that stores constants and address change flags used in 8ilt conversion instructions, 10 is 8VR (Software
eVisible Regrster) /-eS, 1
1 is a constant memory address generation circuit that generates an address to constant memory 8 from the field and operand 1 of the main memory (MMχ1za CAR5), the sign output of manual register 1, and the address change flag bit F output of constant memory output register 3. Each is shown below.

FIG. 4 is a detailed diagram of the constant memory address generation circuit 12 of FIG. 3 and its surroundings. In this example, the constant memory has a constant memory address B bit and a capacity of 256W. The constant memory address generation circuit 12 is configured such that the constant memory address generation circuit 12 is configured as follows. AND gate 15% 16% OR gate 1
It is organized by 7. The address of constant memory 8 is normally given as an 8-bit field output to C8, but depending on the value of the address change flag bit of constant memory output register 3, the sign output of register 1 for one operand is changed to C8.
The structure is such that it can be replaced with the least significant bit of the 8-bit field in 8R5. Note that 8a represents an address change flag field, Bb represents a constant field, and 3a represents an address change flag. Address change 7 lag 3a
KOK field output to C8R5 when is m O#
I Kx Ks Ka Kg Ks Kt, the address of constant memory 8 is the same (Ko KI KI KI
Ka Ks Ks Kt, but when the address change flag 3a is 11', the sign output S of the operand 1 manual register 1 is used.) Ka KI Km Ks Ka
It is modified as KIK88.

Next, regarding the value of the address change hook field of the constant memory 8, the conversion constant that depends on the calculation data D is 1, and the upper 7 bits of the constant memory address are equal and only the lower 1 bit differs in the address field. It can be divided by. A constant that does not depend on the calculation data D is 0, and the upper 7 bits of the constant memory address are equally allocated to addresses that differ only by the lower 1 bit, and the same value is assigned as 2 words.

In FIG. 4, the conversion constant λ when the binary data is positive is stored at the address Q Q + of the constant memory 8, OIH, and the conversion constant λ when the binary data is negative is stored at the address.

Next, the constant reading operation of the conversion command will be explained based on FIGS. 3 to 5. In addition, in Fig. 5, (Ax
) indicates the contents of address As.

(First step) The start address A1 of the conversion instruction is set in the CS address register (hereinafter referred to as C8A) 6 upon activation of the instruction.

(Second step) The next execution address At is set in C8A6, and 08
Contents of next execution address A1 to R5, i.e. operand 1
Read instruction and constant memory address specification (address change flag set') (As! Read. CAR5
The OOH address is set in the field.

(3rd step) Next execution address person to C8R5! , i.e. operand 1 hold instruction and constant memory address specification (Ax
泗1 is read out. Fioo in the field of C8R5
l (address is set. Operand 1 manual register l
Operational data D to be converted is set from the 8VR memory 1O by the K#-i operand 1 read instruction and constant memory address specification (AI). The conversion constant λ or λ is read into the constant memory output register 3, and address change 7 lag 3aij "l" is set.

The OOH address is set in the C8R5 field.

(Fourth step) C8R5's operand l hold instruction and constant memory address input register l are held, and the address change flag 3a is set at the lowest point of the output 00H of the field of C3Rs. Since it is e+1t+, the sign output S of operation case D becomes valid υ and is replaced with the value of the sign bit S.The conversion constant λ or λ according to the sign is read into the constant memory output register 3. .

As explained above, the conversion constant is determined by the fixed T number 2T without branching of the microprogram. In addition, in the case where the constant does not depend on the calculation data, only the least significant bit differs2
Since the same constant is stored in each word, it can be read by IT regardless of whether or not the address change flag is modified.

Effects of the Invention The present invention is configured and operates as described above.According to the present invention, by reading conversion constants that depend on operation data at high speed with a fixed number of T without branching of microinstructions, The overall processing cycle is reduced and pipeline control becomes easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a conventional arithmetic unit of this type, FIG. 2 is an operation time chart of the configuration shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. , FIG. 4 is a block diagram showing a detailed MB7z configuration example of the constant memory address generation circuit shown in FIG. 3 and its peripheral parts, and FIG. 2 is an operation time chart of one embodiment. lagφ operand l input register, 2...-operand 2 manual register, 3 fist/constant memory output register,
4 lives...Arithmetic result register, 511...C8 read register (C8 几入6...CSS address register C8
A), 7th instruction...control memory (CS), S-0, constant memory, 9000 branch circuit, 10@-, SVR memory, ll...Φ main memory (IJM), 12--constant number memory address generation circuit

Claims (1)

[Claims] means for storing calculation data; memory means for storing constants and address change flags necessary for execution of calculations;
and means for modifying the address of the memory means by the value of the means for storing the operation data and the value of the address change flag of the memory means, and obtaining constants required for execution of the operation from the memory means. A computing device characterized by: