JPS5826584B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that adds instruction subcodes to normal instruction codes to increase the number of instruction words, thereby improving performance and ease of use.

More particularly, the present invention relates to a data processing device that uses microprograms to control arithmetic units.

Recently, technology has been adopted to add instruction subcodes to instruction codes in order to increase the number of instruction words for the purpose of improving performance and ease of use.

FIG. 1 shows the format of a command word of a general data processing device.

The S format and SS format 3 in the figure are examples of this.

However, since logic circuit elements have traditionally been used to decipher instruction codes, it has not been easy to change the actual machine when adding new instruction words or changing specifications.

Sometimes changes were not possible and plans to add command words had to be abandoned.

In addition, in data processing devices that use microprograms to control arithmetic units, when an instruction subcode is added to an instruction code, the microprogram is used to test whether or not the subcode is valid. A method is used in which the instruction branches to execution processing, and if the instruction is invalid, branches to invalid instruction processing.

FIG. 7 shows an example of the above test. In FIG. 7, eight steps of the microprogram are used before effective execution begins.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that eliminates the drawbacks of the prior art described above, facilitates addition of instruction words and changes in specifications, and improves the performance of instruction words using instruction subcodes. It is in.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment of a data processing apparatus having an arithmetic unit to which microprogram control is applied.

FIG. 2 shows a block diagram of the data processing device.

1 is the main memory (MS), 2 is the storage control unit (SC)
3 is an instruction control unit (IU) and 4 is an arithmetic unit (EU).

The instruction word is read out from MSl via 5CU2 to IU3, decoded by IU3, and if the instruction requires an operand, it is read out from MSl via 5CU2 at the request of IU3.
Read out by U3.

The instruction word operand prepared by IU3 is sent to EU4 and executed.

As a result of the execution by EU4, if necessary, the calculation result is written to MS1 via 5CU2.

FIG. 3 shows an embodiment of the invention.

301 is an instruction register, 302 is a save register for the 8-bit instruction code of the instruction register 301, 303 is a save register for the 8-bit instruction subcode of the instruction register 301,
304 is a memory DS in which control information of command words is stored.
1, and the 8-bit instruction code of the instruction register 301 is given to the memory 304 as address information via the line 310, and the contents are read out.

The register 306 stores read data from the memory 304, and is composed of three bits: alta2ta3.

The two bits al t a2 represent the classification of each instruction code, and a3 indicates that the instruction code is valid.

When alt82 is “00”, instruction subcode is not used Q”, “01”.

When lT10H is "11", it indicates that the instruction uses the Q+ subcode.

A memory DS2 305 stores instruction control information of the instruction subcode, and the contents of the memory 305 are read by receiving 8 bits of the instruction subcode as address information via a line 311.

A register 307 stores read data from the memory 305 and stores bl, b2 . Consists of 3 bits b3.

When al t a2 is '01', if bl is 1'', that @all subcodes are valid, and bl is uO
If it is u, it indicates that the instruction subcode is invalid.

Similarly, when al 1 a2 is '10', b2 is 111
1Z al, When a2 is '11', if b3 is 1'', it indicates that the instruction subcode is valid, and al
When t a2 is '10' (this b2 is Toll, al
, If b3 is O'' when a2 is '11', it indicates that the instruction subcode is invalid.

Selector 309 moves line 313 to 0'' if a3 is °0''.
Output.

If a3 is 1'', set it to al, and if a2 is 'oo', set it to 1, ? +
If it is 0191, use bl, if it is ulot+, use b2,
If n 11+1, output b3 to line 313.

That is, if the line 313 is 1'', it is a valid instruction code or subcode, and if it is 0'', it is an invalid instruction code or subcode.

402 is a control storage device C8 in which the microprogram used by the arithmetic unit is stored, and 401 is C8402.
An address register 403 is a register that stores read data from the C8402.

The address register 401 has 1 bit each of CI and C2.
It consists of a total of 12 bits: y C3 + C4 and 8 bits C5.

When passing an instruction word from the instruction control unit 3 to the arithmetic unit 4, the start address of the microprogram of the corresponding instruction word is set in the CS address register 401 through the line 314, and processing of the corresponding Q4' word begins.

If the line 313 is "0", it is an invalid instruction, so the selector 308 passes the line 314 to C1, C2, and C3.

Each bit of C4 and all eight bits of C6 are set as 1''.

When the line 313 is °1'' and al l 22 is 'oo', it is a valid instruction that does not use the instruction subcode, and C1*
C2+C3yc4 is '0001'.

The instruction code 8 bits are set in C5 through lines 315 and 314.

When line 313 is °゛1'' and 21, and a2 is 01'', C
1p C2p C3t C4 is '0010', C5 is the instruction subcode set through lines 316 and 314.

When line 313 is °1'' and al y a2 is '10'', C
1, C2, C3, and C4 are set to '0100', and c5 is set to the instruction subcode in the same manner as above.

When line 313 is pa 1'', it is al, and when B2 is '11'', it is C
1, C2, C3.

C4 is set to '0110', and C5 is set to the instruction subcode in the same manner as above.

That is, even if an instruction word that uses an instruction subcode added to an instruction code is a valid code, the start address of the microprogram that processes the '#i◆ word is directly set in the CS address register 401 by the IU3.

The above invention will be further explained by giving examples.

FIG. 4 shows an example of the contents of DSI in the memory 304, and FIG. 5 shows an example of the contents of DS2 in the memory 305.

Each DSI. The address of DS2 is given in 8 bits, but here the 8 bits are divided into upper 4 bits and lower 4 bits, and the address is expressed in hexadecimal notation.

For example, if the 8 bits are '00000001'', it is displayed as (01)16 in hexadecimal.

From Figure 4, B3 of DSl address (00)16 is 0''
Therefore, the instruction code (00) 16 means an invalid instruction code.

Since B3 of address (04) 16 is °゛1'' and al and B2 is 'oo', instruction code (04) 16 is a valid instruction code, which means that it is an instruction that does not use the instruction subtoe. do.

B3 of address (B2) 16 is '1'', al, B2 is '
01'', the instruction code (B2) 16 is a valid instruction code, and is an instruction that uses the instruction subcode.
The validity of the subcode depends on the BL information of DS2.

When searching DS2 using the subcode as an address, it is found from Figure 5 that subcodes (00)16 and (01)16 are invalid because bl is 0'', but (02)16.(03)
)16. It can be seen that (04)16 and (05)16 are valid.

That is, instruction code, subcode (B202) 16,
(B203) 16° (B204) 16 and (B20
5) It can be seen that 16 is valid @now, but other commands are invalid.

Similarly, in address (B5) 16 of -DS1, B3 is T' and al.

Since B2 is '10', instruction code (B5) 16 is an invalid instruction and an instruction that uses a subcode.

Information on b2 of DS2 is searched in the same way, and in the example of FIG. 5, b2 of subcode (01)16 + (02)16 is 1.
'', (B501)16, (B502)1
It can be seen that 6 is a valid@raw code.

Similarly, in the case of #J instruction code B6) 16, B3 is 1
'', 21 + 22 = ``11'', so this is still an instruction that uses an instruction subcode, and the validity of the subcode is determined by searching the b3 bit of DS2.

In this case, it can be seen that only (B601)16 and (B605)16 are valid instructions.

FIG. 6 shows the format of the start address of the microprogram set in the address register 401 of each type of @ instruction.

A more specific example is shown below.

For example, instruction code (B2) 16 y subcode (
02) Assume that 16 @all words are set in the instruction register 301.

(B2)16 t (02)16 are the lines 310,
311 and is saved to save registers 302 and 303.

At the same time, (B2) 1a is (0
2) If 16, it is sent as the DS2 address.

DS], the information of the address (B2>16) is read out and set in the register 306.

In this case, according to FIG. 4, al, B2. B3 is '011''
becomes.

Information at address (02) 16 is read from DS2 and set in register 307.

In this case, according to FIG. 5, bl, b2. b3 is '110''
It is.

B3 is 1'' and al; B2 is 0'', so bl is output on line 313.

Since b1 is now ``1'', line 313 is also 1''.

Next, in the selector 308, the line 312 is '01' and the line 313 is '01'.
is 1'', the upper 4 bits of the data line 314 are 0010, and the lower 8 bits are the instruction subcode (o
2) to is output, these 12 bits are set in the address register 401 at the start of the operation in the arithmetic unit, and the execution process of immediate execution ◆ begins.

If the instruction code and @command code are invalid (undefined code), "0111" is set in the upper bits and a specific pattern of "1 per" is set in the lower 8 bits.

In this way, if the code is invalid, it can be skipped to a unique specific address regardless of the contents of the invalid code, and there is no need to prepare a microprogram to deal with the invalid code.

The structure of the microprogram in this case is shown in FIG.

A comparison with FIG. 7 of the prior art shows that the test time for subcodes can be significantly reduced.

As explained above, if the present invention is used, instruction words can be easily added or changed without changing the hardware by storing them in the instruction control information memory, and subcodes can be added to arbitrary instruction codes. The number of command words can be increased by

Furthermore, even instructions that use subcodes can be processed as quickly as instructions that do not use subcodes.

[Brief Description of the Drawings] Fig. 1 is a diagram showing the format of a command word, Fig. 2 is a schematic functional block diagram of a data processing device to which the present invention is applied, and Fig. 3 is a diagram showing an embodiment of the present invention. , FIG. 4 is a diagram showing an example of contents written in DS1, FIG. 5 is a diagram showing an example of contents written in DS2, and FIG. 6 is a diagram showing control when each instruction word is transmitted to the arithmetic unit. A diagram showing the start address of a microprogram in a storage device, FIG. 7 is a diagram showing an example of a conventional microprogram using an instruction code and an instruction subcode, and FIG. 8 is a microprogram using the present invention. It is a figure which shows an example. 3... Advance command control unit, 4...
Arithmetic unit, 301...Instruction register, 30
2 and 303... Save register, 304 and 305... Memory, 306 and 307...
...Registers, 308 and 309...Selector, 401...Address register, 402
...Control storage device.

Claims (1)

[Scope of Claims] 1. A data processing device that performs instruction control by adding an instruction subcode to an instruction code to increase the number of instruction words, which stores instruction control information and specifies that the instruction code is given as an address. a second memory that stores instruction control information and outputs specified instruction control information given the instruction subcode as an address; and the first memory. Based on the command control information output from the specific pattern and the second
a first selector that outputs any one of the contents of at least one bit of instruction control information output from the memory; and an output of the instruction control information output from the first memory and the first selector. and a second selector that outputs any one of the instruction code, the instruction subcode, and a specific pattern based on the above, and provides it as an address of a control storage device storing the microprogram. Processing equipment. 2 The above instruction control information includes information indicating whether the instruction word is valid in the first memory, information indicating whether the instruction word uses a subcode, and information indicating whether the instruction word uses a subcode, and the instruction word that views the subcode. information indicating the format, and the second
2. The data processing device according to claim 1, wherein information indicating whether or not an instruction subcode is valid is stored in the memory, and invalid instruction codes and invalid instruction subcodes are detected at high speed. 3. The data processing according to claim 2, wherein the second selector provides only one specific pattern as the address of the control storage device when the instruction code and instruction subcode are invalid. Device. 4 When outputting the instruction code or instruction subcode, the second selector adds a specific pattern to the instruction code or instruction subcode according to the instruction control information from the first memory and outputs the instruction code or instruction subcode. A data processing device according to any one of claims 1 to 3.