JPH0587881A - Data log circuit - Google Patents

Abstract

PURPOSE:To carry out the writing into a pin memory without using a delay line for each channel and accommodate a large quantity of fail information in a pin memory having a small capacity. CONSTITUTION:A plurality of blocks 1A-1C connected with a DUT 10 and gates 2 and 3 which receives the output of each gate 22 in the blocks 1A-1C and generate, the write-in signals in a fail cycle are provided. Further, a fail block memory 4 which receives the output of each gate 22 in the block and a LOG address generator 5 for automatically changing the address of the fail block memory in synchronization with the write-in signal are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data log circuit for storing fail cycle and pin fail information in an integrated circuit tester.

[0002]

2. Description of the Related Art Next, a configuration of a data log circuit according to the prior art is shown in FIG. The timing chart of FIG. 4 is shown in FIG. Reference numeral 10 in FIG. 4 is a device under test (hereinafter, DU).
11) to 13 are decision devices, 21 is a pin memory,
Reference numeral 22 is a gate, 26 to 28 are delay lines, 31 to 33 are gates, 3 is a gate, 5 is a log address generator, 7 is a test cycle counter, 8 is a cycle memory, and 9A to 9C are gates.

A 0 address is set in the log address generator 5. The outputs from the DUT 10 are the decision devices 11 to 13
Is determined by. The determiner 11 generates "1" in the cycle N + 1 in FIG. The output of the determiner 11 controls the write synchronization signal 5A by the gate 22 and the gate 3, and generates the write signal 5B at the cycle N + 1 in FIG. The log address generator 5 generates the next address "1" at the timing of the rising edge of the write signal 5B.

The write signal 5B and the output 5C of the log address generator 5 are also given to the pin memory 21. The outputs of the decision units 11 to 13 are given to the delay lines 26 to 28,
The write signal 5B and the output 5C of the log address generator 5 are provided with a necessary delay amount up to the time and then given to the pin memory 21. The output of the delay line 26 is given to the pin memory 21, and the pin memory 21 stores "1" in the cycle of N + 1 and simultaneously stores "0" of the determination outputs of the determiners 12 and 13 through the delay lines 27 and 28. At the same time, N + 1 is output from the test cycle counter 7 to the cycle memory 8
Memorized in.

Further, for example, in the next N + 2 cycle, the write signal 5B is similarly generated by the determination signal generated from the determination device 12, and the log address generator 5 generates the next address "2" at the timing of the rising edge thereof. To do. "0", "1", and "0" are stored in the pin memory 21 through the delay lines 26 to 28 as the determination outputs of the determiners 11 to 13, respectively.

When reading, the address "0" is set in the log address generator 5. Next, read signal 5
By setting F to “0” and reading the pin memory 21 and the cycle memory 8, it is possible to know in which cycle which channel failed. In the example, it can be seen that 1 channel is failed in N + 1 cycles and 2 channels are failed in N + 2 cycles.

[0007]

In the conventional data log circuit, the gate 3, the log address generator 5, the test cycle counter 7, the cycle memory 8, and the gates 9A to 9C are the decision units 11 to 13, the pin memory 21, and the gate 22. , The gates 31 to 33 are usually separate units, so that the output 1AC of the gate block 22, the write signal 5B, and the output 5C of the log address generator 5 are connected via cables. The output 1AC of the gate 22 is given to the gate 3 with a delay of the delay amount D of the cable. Write signal 5B generated from gate 3, output 5 of log address generator 5
Similarly, C is delayed by the delay amount D and given to the pin memory 21 as 5Ba and 5Ca, respectively.

Therefore, the write signal 5B and the output 5C of the log address generator 5 are given to the pin memory with a delay of twice the delay amount D with respect to the outputs of the determiners 11 to 13.
Between the determiners 11 to 13 and the pin memory 21, it is necessary to insert the delay lines 26 to 28 having twice the delay amount D for each channel. In particular, if the system cycle becomes faster, the signal cannot be accurately transferred unless the delay lines having a small delay amount due to the characteristics of the delay line are connected in multiple stages.

In modern systems, a 10 ns delay line
It may be connected in stages. Further, in order to change the pin memory addresses of all channels every time a failure occurs in another channel, it is necessary to increase the pin memory capacity in a device equipped with multiple channels.

It is an object of the present invention to provide a data log circuit for writing to a pin memory without using a delay line for each channel and storing a large amount of fail information with a small capacity pin memory.

[0011]

In order to achieve this object, according to the present invention, a plurality of judging devices 11 to 13 connected to the DUT 10 and a pin memory 21 having the outputs of the judging devices 11 to 13 as inputs, A gate 22 that receives the outputs of the determiners 11 to 13 and that generates a write signal only during a fail cycle, and a pin memory 2 that synchronizes with the read and write signals
One block is configured with the pin memory address generator 25 that automatically changes the address of 1 and multiple blocks are
Gates 2 and 3 which are connected to the UT 10 and which receive the output of each gate 22 as an input and generate a write signal only during a fail cycle.
And a fail block memory 4 that receives the output of each gate 22 in the block, and a log address generator 5 that automatically changes the address of the fail block memory 4 in synchronization with a write signal.

[0012]

The structure of the data log circuit according to the present invention is shown in FIG. 2 is a timing chart of FIG.
An example of memory writing will be described with reference to FIG. 1A of FIG.
1C is a block, 2 is a gate, 4 is a fail block memory, and the others are the same as in FIG. Block 1
Each of A to 1C has the same configuration, and the determiner 11
˜13, pin memory 21, gate 22, gate 23, gate 24, pin memory address generator 25, gate 31
Is composed of .about.33. The determiners 11 to 13, the pin memory 21, the gate 22, and the gate 31 in the blocks 1A to 1C
33 are the same as in FIG. A plurality of blocks 1A to 1C are connected to the DUT 10. 1 does not have the delay lines 26-28 of FIG.

The outputs from the DUT 10 are the decision devices 11-13.
Is determined by. The outputs of the determiners 11 to 13 are “1” in the case of failure. The outputs of the determiners 11 to 13 are given to the data input terminal of the pin memory 21. Judgment device 11-13
When any one of the outputs of "1" is "1", the gates 22 and 2
The write signal 1AE is given to the write enable terminal of the pin memory 21 by 3 and the write synchronization signal 1AB. Further, the write signal 1AE is applied to the pin memory address generator 25 through the gate 24, and the next address is generated at the timing of the rising edge of the write signal 1AE in FIG.

Output 1A of pin memory address generator 25
F is given to the address of the pin memory 21. When the output 1AC of the gate 22 is "0", the write signal 1
AE does not occur, and the output of the pin memory address generator 25 does not change.

On the other hand, the output 1AC of the gate 22 is given to the data input terminal of the fail block memory 4 and the gate 2. When the output of the gate 2 is "1", the write signal 5B is given to the write enable terminal of the fail block memory 4 by the gate 3 and the log write cycle signal 5A.

The log address generator 5 generates the next address at the timing of the rising edge of the write signal 5B. The output of the log address generator 5 is given to the fail block memory 4 and the cycle memory 8. When the output of the gate 2 is "0", the write signal 5B is not generated and the log address generator 5 does not generate the next address.

At the time of reading, an initial value "0" is set in the pin memory address generator 25 and the log address generator 5. The log read signal 5D is set to "0" to read the fail block memory 4. Next, set the output terminal 5E to "1".
Read signal 1AA ~ corresponding to the block from which
When one of the 1CAs is set to "0" and the pin memory 21 is read out, the gate 24 simultaneously reads out the read signals 1AA to 1C.
At the timing of the rising edge of A, the output of the pin memory address generator 25 automatically generates the next address.

The read signals 1AA to 1CA are not given to the block from which "0" is read. As described above, the fail information can be read from the pin memory of each block, and the cycle and channel in which the failure has occurred can be known.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an operation example of the data log circuit will be described with reference to FIG. A time chart is shown in FIG. 2 and an example of memory writing is shown in FIG. FIG. 3 shows the output state of the determiner, the write data of the pin memory of each block, the write data of the fail block memory, and the write data of the cycle memory at the time chart of FIG. In the semiconductor test equipment, one block consists of 32 to 64 channels. “0” is set as an initial value in the pin memory address generator 25 and the log address generator 5.

The outputs from the DUT 10 are the decision devices 11-13.
Is determined by. The determiners 11 to 13 make a determination for each test cycle, "1" for fail and "0" for pass.
Is output. The outputs of the determiners 11 to 13 are pin memories 21.
Is connected to the gate 22. For example, when the output of the determiner 11 becomes “1” in N + 1 cycles, the write signal 1AE is generated from the gate 23 and applied to the write enable terminal of the pin memory 21. Write signal 1AE is applied to gate 24
Is also given to the pin memory address generator 25 through
The next address "1" is generated at the timing of the rising edge of the write signal 1AE. Therefore, the pin memory 2
1 is “1” in D10 of address 0 in the cycle of N + 1, D
Write "0" in 11 and D12. No write operation is performed in the cycle of N; N + 2.

On the other hand, the OR signal 1AC becomes the write signal 5B by the gates 2 and 3 and is given to the write enable terminals of the fail block memory 4 and the cycle memory 8. Since the OR signal 1AC is "1" in the N + 1 cycle, the write signal 5B is generated in the N + 1 cycle.

Further, since the OR signals 1AC to 1CC are also applied to the fail block memory 4, "1" is written in D0 in the cycle of N + 1, and at the same time, the output N + 1 of the test cycle counter 7 is written in the cycle memory 8. Get caught. The write signal 5B is also applied to the log address generator 5 through the gate 3 to generate the next address "1" at the timing of the rising edge of the write signal 5B.
In the N + 2 cycle, "1" is written in D1 of the address "1" by the OR signal 1BC from the block 1B.

Next, the case of reading will be described. “0” is set as an initial value in the pin memory address generator 25 and the log address generator 5. The read signal 5D is set to "0" to read the fail block memory 4. In the example, the gate 6A outputs "1" to the output terminal 5E. At the same time, the cycle memory 8 failed from the cycle memory 8 N + 1
Is read.

Next, the read signal 1AA of the block 1A
Is set to "0", the pin memory 21 is read, and the gate 31
"1" is output to the output terminal 1AD from the channel 1
Is read as a fail. The read signal 1AA is connected to the pin memory address generator 25 through the gate 24, and the output of the pin memory address generator 25 generates the next address at the timing of the rising edge of the read signal 1AA.

Next, the address "1" is set in the log address generator 5, and the fail block memory 4 and
The cycle memory 8 is read, and then the block 1B is read. By repeating the above, the cycle in which the failure has occurred and the channel can be known.

[0026]

According to the present invention, since writing to the pin memory is independent for each block, the writing is performed in the shortest time, and therefore it is necessary to use a multistage delay line between the determiner and the pin memory. Absent. Further, it becomes possible to store a large amount of fail information with a small capacity pin memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data log circuit according to the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a diagram showing an example of memory writing in FIG. 1.

FIG. 4 is a configuration diagram of a data log circuit according to a conventional technique.

FIG. 5 is a timing chart of FIG.

[Explanation of symbols]

 1A to 1C block 2 gate 3 gate 4 fail block memory 5 log address generator 6A to 6C gate 7 test cycle counter 8 cycle memory 9A to 9C gate 10 DUT (device under test) 11 to 13 decision device 21 pin memory 22 gate 23 Gate 24 Gate 25 Pin Memory Address Generator

Claims (1)

[Claims] 1. A plurality of judging devices connected to a device under test (10), and a pin memory (21) having inputs of the judging device outputs.
And a first gate (22) which receives the output of the judging device as an input and generates a write signal only in a fail cycle, and a pin memory address which automatically changes the address of the pin memory (21) in synchronization with the read and write signals. One block is composed of the generator (25), a plurality of the blocks are connected to the device under test (10), the output of each of the first gates (22) is used as an input, and only the fail cycle is written. A second gate (2) for generating a signal,
(3), a fail block memory (4) that receives the output of each first gate (22) in the block, and a log that automatically changes the address of the fail block memory (4) in synchronization with the write signal. A data log circuit comprising an address generator (5).