JPS61153737A - Data processor - Google Patents

Abstract

PURPOSE:To evaluate completely the execution of a micro-instruction by inputting an address data and a signal for indicating a branch direction to a specified trace memory after initializing, and displaying them effectively at a prescribed bit position in accordance with a non-condition branch and a condition branch. CONSTITUTION:The micro-instruction indicated by an address register 2 which is brought to an updating control by a sequence controlling circuit 4 is read out of a control storage 1 and executed by an operating circuit 3, the width of the number of bits of a trace memory 5 is equalized to the maximum number of branch directions which is held by a condition branch function of the circuit 4, and its capacity becomes the capacity of the same number of words as that of the storage 1. Also, '0' clear can be executed to all the words of the memory 5 by a trace memory write controlling circuit 6, and also '1' can be written to the bit corresponding to the signal for indicating the branch direction from the circuit 4. In this state, when the micro-instruction is a non-condition branch, '1' is written to the bit '0' of the memory 5, and when said instruction is a condition branch, '1' is written to the prescribed bit position for indicating the branch direction of the memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data tracing method for a microprogram control device in a data processing device.

[Conventional technology]

Conventionally, in a microprogram control device.

In order to know to what extent microinstructions are actually used in the operating state, or whether all microinstructions are actually executed when running an evaluation test program, a first-order method is used. He had been hired.

That is, in the control memory that stores microinstructions.

Provide a means for each word to indicate whether or not that address has been accessed even once, and evaluate! After executing the program, each word of control memory is examined to find that microinstructions at addresses that were not accessed remained unexecuted.

[Problem that the invention seeks to solve]

However, with this method, it cannot be said that the evaluation of the accessed microinstruction has been completed.

For example, if we consider a microinstruction sequence as shown in Figure 4, if we pass through A→B-+C and D-+E-)F, then all microinstructions from A to F have been executed. become. However, in reality A→E−+C or A −+ BE −+ p′ or D 4 E −+
There are classes such as C, and these paths must also be evaluated. Therefore, the evaluation using the conventional method was insufficient.

[Means to Solve the Problem] According to the present invention, a control memory for storing microinstructions, an address register for giving an address to the control memory, and a memory for controlling the control memory specified by the address register are provided. In a data processing device consisting of an arithmetic unit controlled by a microinstruction read from a storage location and a sequence control unit that controls address updating of the address register, the maximum branch of the conditional branch function of the sequence control unit is a trace memory having a width of a number of bits equal to the number of directions and a capacity of the same number of words as the control memory;
means for clearing all words of the trace memory to 0; means for reading and displaying the trace memory; and address data given from the address register after all words of the trace memory are cleared to zero by the 0297 means in advance. A signal indicating the branch direction given from the sequence control unit is input, and when the microinstruction corresponding to the address data is an unconditional branch, °1" is written only to a predetermined bit position, and when it is a 2-conditional branch. There is obtained a data processing device characterized in that it is provided with means for writing ``1'' only in a bit position designated by a signal indicating a branch direction determined by the conditions at the time of execution of the microinstruction.

[Effect]

According to such a configuration, information indicating the branch direction is stored in the trace memory, taking into account the conditional branch of the microinstruction, so that a more complete evaluation of the execution of the microinstruction can be performed.

〔Example〕

Next, two embodiments of the present invention will be described in detail with reference to two drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. In fig.

1 is a control memory for storing microinstructions; 2 is an address register indicating the address of the microinstruction to be executed in the control memory 1; 3 is an arithmetic circuit that is controlled by microinstructions read from the control memory 1 and performs targeted data processing;
Reference numeral 4 denotes a sequence control circuit that controls updating of address values in order to control the execution sequence of microinstructions for the address register 2. 5 is a trace memory having a width of bits equal to the maximum number of branch directions of the conditional branch function of the sequence control circuit 4 and a capacity of the same number of words as the control memory 1; 6 is a trace memory for all words of the trace memory 5; The bit corresponding to the function to clear O and the signal indicating the branch direction sent from the sequence control circuit 4 is set to “1”.
Trace memory write control circuit with a function to write “
is a read/display circuit having a function of reading and displaying the contents of each address of the trace memory 5. 8 is still address register 2. This is an address selector that selects one of the address data of the trace memory 5 sent from the trace memory write control circuit 6 and the read display circuit 7.

Next, the operation of the embodiment of the present invention will be explained in order. However, in the following description, it is assumed that the sequence control circuit 4 has a conditional branching function in a maximum of four directions. Therefore, the bit width of the trace memory 5 is 4 bits, which will be referred to as bits 0, 1, 2, and 3 in that order.

If the microinstruction currently being executed is an unconditional branch, the process will be as follows. When the sequence control circuit 4 issues an instruction to store the next address in the address register 2 via a path 11, it also sends a signal indicating an unconditional branch to the trace memory write control circuit 6 through all nodes 12. In the trace memory write control section 6.

At this time, in order to write the bit OK "l" in the storage location of the trace memory 5 specified by the address data sent through the node 10, the address selector 8, and the path 24, a write instruction is sent via the paths 15 and 16. and send 1” data.

Next, the case where the microinstruction currently being executed is a conditional branch will be explained. If the conditional branch is in two directions, there will be signals indicating two types of branching directions depending on the conditions, and if there are four directions, there will be signals indicating four types of branching directions depending on the conditions.

It is sent to the trace memory write control circuit 6 via path 12. In the case of two-way branching, either bit O or bit 1 is selected depending on the condition, and the write instruction and data of °1'' are sent via paths 15 and 16 or /J paths 17 and 18. and written to the bit position of the corresponding address in trace memory 5. Not yet.

In the case of 4-way branching, beep) 0, 1. -2.3 is selected depending on the condition, and similarly, a write instruction and data 1'' are sent through a set of paths 15 to 22, and the trace memory 5 is Written to the bit position of the corresponding address.

With this procedure, data of 1'' is written into the corresponding bit position of the trace memory 5 every time the microinstructions are executed sequentially.

Next, as a concrete example, consider the flow shown in Figure 2,
A case where the trace result is as shown in FIG. 3 will be explained. In these figures, a.

~a7 indicates an address, and FIG. 3 shows the contents of the trace memory 5.

Looking at the bit 0 column, address a. -a7 are all '1
” has been written, so the address ao of control memory 1 is
It can be seen that all microinstructions at the storage location indicated by ~a7 are executed. but.

Looking at the line of address a1, bit 2 is '0'
It remains as it is. This is when the microinstruction at address al is executed, from address a1 to address a among four-way branches.
This indicates that there is no condition that would cause the path to branch to 4, and that path was not taken. Therefore, in this example + ao
It can be seen that the operation confirmation when executing the path -+a1-+a4→a7 has been omitted.

In this way, by examining the contents of the trace memory 5, unevaluated paths can be detected.

2. In this embodiment, the contents of the trace memory 5 are displayed on the readout display circuit 7, but it is not possible to calculate the expected value of the contents of the trace memory by processing the microprogram file. Since it is easy, a comparison means for comparing the expected value and the contents of the trace memory may be provided in place of the readout display circuit 7 to automatically perform the comparison check.

〔Effect of the invention〕

As described above, the present invention has the advantage that by collecting information indicating the branch direction of microinstructions, microinstruction execution can be evaluated more completely.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing device according to the present invention, FIG. 2 is a diagram showing a specific flow example for explaining the present invention, and FIG. Figure 4 shows an example of the contents of the trace memory for the flow of
The figure is a diagram showing a microinstruction sequence to explain the conventional drawbacks. 1...Control memory, 2...Address register, 3...
- Arithmetic circuit, 4... Sequence control circuit, 5... Trace memory, 6... Trace memory write control circuit. 7...Readout display circuit, 8...Address selector. Figure 3

Claims (1)

[Claims] 1. A control memory that stores microinstructions, an address register that provides an address to the control memory, an arithmetic unit that is controlled by the microinstruction that is read from a storage location in the control memory specified by the address register, and the address In a data processing device comprising a sequence control unit that controls address updating of registers, the sequence control unit has a width of a number of bits equal to the maximum number of branch directions of a conditional branch function possessed by the sequence control unit, and the same number of bits as the control memory. A trace memory having a capacity of the number of words, an initial setting means for the trace memory, a means for reading and displaying the contents of the trace memory, and after initializing the trace memory in advance by the initial setting means, Address data given from the address register and a signal indicating a branch direction given from the sequence control section are input, and when the microinstruction corresponding to the address data is an unconditional branch, a valid indication is displayed in a predetermined bit position. 1. A data processing device comprising means for executing a conditional branch and displaying validity at a bit position indicated by a signal indicating a branch direction determined by the conditions at the time of execution of the microinstruction.