JPS6198453A - Test device - Google Patents

Abstract

PURPOSE:To obtain an unpassed address in a test of software by storing a program branch instruction previously in a memory and also the address of the branch instruction of an executing program in another memory. CONSTITUTION:When the execution of a test program is indicated, a control circuit 6 indicates the execution of a microinstruction. Then an instruction executing part 12 executes a program and at the same time the contents of an address register 11 are written to a tracer memory 2. Hereafter the writing is carried out successively up to the full capacity of the memory 2. Then the contents of the memory 2 are sent to a service processor 7 by a reading circuit 4. While the contents of the memory 2 are stored in a magnetic disk device 9. Then the circuit 6 starts execution of the microinstruction, and the memory 2 stores the microbranch instruction address. This instruction address is stored also in the device 9. Then the processor 7 sets each information bit corresponding to each microinstruction address and extracts the branch instruction address stored in the memory 9 to reset the relevant information bit as long as it is within a prescribed range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program-controlled information processing device or software testing device.

[Conventional technology]

As information processing equipment becomes more sophisticated, complex, and multifunctional,
It has become increasingly important to test whether the functions, performance, etc. of developed information processing equipment (hereinafter referred to as "developed equipment") satisfy the initial goals, and various testing methods have become necessary. A typical test method is a test program, which is executed by the development equipment.

The developed device is tested by checking whether it produces the expected results. Incidentally, since the quality of the developed device is greatly influenced by the items to be tested in the test program, determining the test items has become a very important technique. Conventionally, test items have been determined from the specifications of the developed equipment based on the experience and intuition of engineers.

[Problem that the invention seeks to solve]

However, because the determination of test methods and test items, such as the test program, relied heavily on the experience and intuition of engineers, essential test items were often left out. Unfortunately, the developed equipment was shipped without sufficient testing.

Another drawback was that the pursuit of completeness in testing led to a huge number of duplicate test items, resulting in uneconomical testing.

Furthermore, not only testing of information processing devices but also testing of programs such as operating systems had exactly the same drawbacks.

An object of the present invention is to provide a test device that can completely and economically test programs for microprogram-controlled information processing devices, operating systems, and the like.

[Means for solving problems]

The test device of the present invention stores in advance a program branch instruction of a program-controlled information processing device or software in a first storage means, and stores seven program branch instructions of the information processing device or software that are executed by a logic device according to a test program. (The address is stored in the tracer memory, and when each address is stored in the full capacity of this tracer memory, the stopping means stops the execution of the program instruction, and then the reading means reads out the contents of the tracer memory and services it.) After the processor stores the instructions in the second storage means, the initiating means resumes execution of the program instructions and repeats the same operation, so that all the addresses of the executed program branch instructions are stored in the second storage means. When the test is completed, the service processor calculates an unpassed address, which is the address of a program branch instruction that has not been executed, from the respective addresses stored in the first storage means and the second storage means, and calculates the unpassed address. The output means outputs.

〔Example〕

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a blow diagram of a test device according to an embodiment of the present invention. The logic device 1 executes a microprogram instruction of the information processing device to be tested according to this embodiment, and has an instruction address register 11 that specifies the address of the microinstruction.
, an instruction execution unit 12 that executes a microinstruction, an address update circuit 13 that updates the contents of the instruction address register 11 each time the execution of each microinstruction is completed, and an instruction execution unit 1
Gate circuit 1 outputs the address of a micro branch instruction when the micro branch instruction is executed in 2, and outputs nothing when an instruction other than the micro branch instruction is executed.
4. Tracer memory 2 is a memory for storing micro branch instruction addresses executed by logic device 1, and consists of 1024 words. The write circuit 3 and the read circuit 4 are controlled by a control circuit 6 to write the micro branch instruction address to the tracer memory 2 and read the micro branch instruction address from the tracer memory 2, respectively. This indicates the word in the tracer memory 2 when writing to the tracer memory 2 or when reading from the tracer memory 2. The control circuit 6 causes the instruction execution unit 12 to start executing microinstructions according to instructions from the service processor 7, and when the contents of the address register 5 overflow, the instruction execution unit 1
2, and further controls the write circuit 3 and the read circuit 4 to write to or read from the tracer memory 2, and when the writing of 1 word or reading of 1 word is completed, the address is Add 1 to the contents of register 5. The service processor 7 stores the contents of the tracer memory 2 read by the reading circuit 4 in the magnetic disk device 9, and further stores the micro branch instruction address that is not executed by the instruction execution unit 12 (hereinafter referred to as the unpassed micro branch instruction address). The display device 8 that calculates
The address of a microbranch instruction within a microprogram to be executed by the logic device 1 is stored in advance in the magnetic disk device 9. This micro branch instruction address group is
When creating a micro program, each instruction of the micro program is decoded using a separate information processing system, and only the address of the micro branch instruction is obtained and stored in the magnetic disk device 9.

The operation of this embodiment will be explained below.

First, the inspector inputs an instruction to start executing the test program from the input section of the display device 8, and this instruction is transmitted to the control circuit 6 via the service processor 7. The control circuit 6 initializes the contents of the address register 5 to 0, and the write circuit 3
After enabling the read circuit 4 and disabling the read circuit 4, the instruction execution section 12 of the logic device 1 is instructed to start executing the microinstruction.

Then, in the instruction execution unit 12, a microprogram corresponding to each instruction of the test program is activated. That is,
The microinstruction address to be executed is set in the instruction address register 1, and the microinstruction at this microinstruction address is decoded and executed by the instruction execution unit 12. by the way,
In parallel with the micro-instruction execution in the instruction execution section 12, the contents of the instruction address register 1 are transmitted to the gate circuit 14, and when the instruction execution section 12 executes the micro-branch instruction, the contents of the instruction address register l are transmitted to the gate circuit 14. is written to the word of the tracer memory 2 indicated by the address register 5 via the gate circuit 14 under the control of the write circuit 3, and furthermore, the contents of the address register 5 are incremented by 1 by the control circuit 6. When the instruction execution unit 12 finishes executing the microinstruction, the address update circuit 13 updates the contents of the instruction address register 11 to the address of the microinstruction to be executed next, and the instruction execution unit 12 updates the microinstruction at the updated address. The instruction is executed, and only when this instruction is a micro branch instruction, the write circuit 3 writes the updated address into the word of the tracer memory 2 indicated by the address register 5.

In this way, the executed microinstruction addresses are sequentially written into each word of the tracer memory 2. and,
When all words (1024 words) of the tracer memory 2 are written, the contents of the address register 5 consisting of 10 bits will overflow, so the control circuit 6 stops the execution of microinstructions in the instruction execution unit 12 and The service processor 7, which received the 0 notification, instructs the control circuit 6 to read the tracer memory 2, and the control circuit 6 initializes the contents of the address register 5 to O, and then executes the write circuit. 3 is disabled and readout circuit 4 is enabled. When the read circuit 4 reads the contents of the word of the tracer memory 2 indicated by the address register 5 and sends it to the service processor 7,
The contents of the address register 5 are incremented by 1 by the control circuit 6, and the reading circuit 4 performs reading again. In this way, when the contents of all the words in the tracer memory 2 are sent to the service processor 7, the service processor 7 stores the read contents of the tracer memory 2 in the magnetic disk device 9.

Next, the control circuit 6 again sets the contents of the address register 5 to 0, enables the write circuit 3, disables the read circuit 4, and instructs the logic device 1 to start executing the microinstruction. Then, in a manner similar to the above-described operation, once the micro branch instruction addresses are stored in all words of the tracer memory 2, these micro branch instruction addresses are stored in the magnetic disk device 9 under the control of the service processor 7.

As described above, all the micro branch instruction addresses executed by the test program for the logic device 1 are stored in the magnetic disk drive 2f9.

Now, when the execution of the test program for the logic device 1 is completed, the examiner inputs the unpassed micro-branch instruction address calculation command C and the upper limit value H and lower limit value of the micro-instruction address from the input section of the display device 8. The service processor 7 calculates an unpassed micro-branch instruction address within the range from the lower limit value of the input micro-instruction address to the upper limit value H.

The process by which the service processor 7 calculates the unpassed microinstruction address will be described below with reference to chart 70 in FIG.

First, the service processor 7 has internal information bits Bj corresponding to all microinstruction addresses.
Each iC information bit corresponding to each microinstruction address in the input range from the lower limit value to the upper limit value H1 is set to "l" (process 21).Next, @K disk device 9 Process 22) to extract from the micro branch instruction address Po corresponding to the micro branch instruction address Pili = 0 stored in advance in 22), and whether or not this micro branch instruction address Pi is within the range from the lower limit value to the upper limit value H. (Process 23), and if it is within the range, set "information bit B" corresponding to the micro branch instruction address Pi to "O" (Process 24).
, if it is outside the range, do nothing, add 1 to the value of i, and use it as a new i. Determine whether the total number has been reached (process 26). If i has not yet reached the total number m, the above-described process 23.
24.25.28 will be held. In this way, processes 23, 24, 25, 28 are repeated until i reaches the total number m. i reaches the total number m, that is, the micro branch instruction 7 previously stored in the magnetic disk device 9)'
Iy , a process 27) of extracting from the micro branch instruction address QO corresponding to the micro branch instruction address Qkt-k = 0 stored in the magnetic disk device 9 by the execution of the test program, the micro branch instruction address Qk is changed from the lower limit value to the upper limit value. It is determined whether it is within the range up to the value H (processing 28), and if it is within the range, the information pitch hBj corresponding to the micro branch instruction address Qk is set to "l" (processing 29),
If it is outside the range, do nothing, add 1 to the value of and use this as a new k (30), and this k becomes the micro branch instruction address Qk stored in the magnetic disk device 9.
It is determined whether the total number n has been reached (processing 31). If k has not yet reached the total number n, the above-mentioned processing 28.29.30. is performed for the next micro branch instruction address Qk.
31 will be carried out. In this way, processing 28.29.
30.31 is repeated until k reaches the total number n. k
reaches the total number n, that is, all the micro branch instruction addresses Qk stored in the magnetic disk device 9 are taken out, determined, and correspond to each micro branch instruction address Qk within the range from the lower limit value to the upper limit value H. Information bit B
When j is set to "l", the value of information bit Bj is set to the lower limit value of the microinstruction address and the corresponding information bit Bj)
The microinstruction address corresponding to the information bit Bj is It is determined that it is a micro branch instruction address and an unpassed micro branch instruction address, and this micro branch instruction address Pi is output to the display device 8 (process 30. When the value of information bit Bj is 0)
If not.

It is determined that the microinstruction address corresponding to information bit Bj is the address of an instruction other than a microbranch instruction or the address of an already executed microbranch instruction, and the process proceeds directly to the next process. Add 1 to the value of j and make it a new j (Process 35), and determine whether this j is greater than the subscript of information Pick) Bh corresponding to the upper limit value H (Process 3B). If not greater than h, perform the above process 33.34.35 for the next information bit Bj
．． 36 is performed, thus processing 33.34
．． Steps 35 and 36 are repeated until j becomes greater than h. When j becomes larger than h, the information bit B1 corresponding to the lower limit value changes to the information bit Rh corresponding to the upper limit value H.
It is determined that all the values of the information Bj) up to y) have been checked, and the process of calculating the unpassed micro branch instruction address is completed.

Finally, the unpassed micro branch instruction address calculated as described above is displayed on the display section of the display device 8.

By the way, since addresses are not branched by instructions other than branch instructions, by checking whether each micro-branch instruction address has been passed, it is possible to distinguish between tested instructions and untested instructions among the program instructions. The unpassed micro-branch instruction address is the address of the micro-branch instruction that has not been tested in the test program of logic device 1.
Iga. Adding a new test program that passes the branch instruction 7 dos 1/s, or using other alternative methods 1, such as testing from a panel installed in the logic device l or testing by inserting a pseudo fault into the logic device l. By performing this processing, the quality of the information processing device can be improved.

In this embodiment, the logic device 1 executes the microprogram instructions of the information processing device, but by executing the program instructions of general software.

It is also possible to test software.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to completely and economically test microprogram-controlled information processing devices or software such as operating systems, thereby improving the quality of information processing devices and software. becomes possible.

[Brief explanation of drawings]

No. 1'5 Invention 0-1 Embodiment'''g''6' Testing device 07
! The lock diagram, FIG. 2 is a flowchart of the untraversed micro branch instruction address calculation process of the service processor 7 of FIG. Logic device 2... Tracer memory 3... Write circuit 4... Read circuit 5... Address register 6... Control circuit 7... Service processor 8... Display device 9... ...Magnetic disk device 11...Instruction address register 12...Instruction execution unit 13...Address update circuit 14...Gate circuit FIG.

Claims (1)

[Scope of Claims] A test device for testing a program-controlled information processing device or software, comprising: a logic device that executes a program instruction of the information processing device or software; and an address of a program branch instruction of the information processing device or software. a first storage means for storing in advance the program branch; a memory comprising a plurality of entries for storing the address of the program branch instruction each time the program branch instruction is executed in the logic device; stopping means for stopping the execution of a program instruction of the logic device when each address of an instruction is stored; reading means for reading the contents of all entries of the memory; and a second means for storing the contents of all entries of the memory. storage means for starting the execution of the program instructions of the logic device; and when the stop means stops the execution of the program instructions of the logic device, the reading means reads the contents of all entries in the memory. and storing it in the second storage means,
After the test is completed by repeating the same operation by the start means and the stop means, the address of the program branch instruction stored in advance in the first storage means and not stored in the storage means is stored in the program branch instruction. A test device comprising: a service processor that calculates an unpassed address; and an output means that outputs the unpassed address calculated by the service processor.