JPH0272440A - Observation system for program executing step - Google Patents

Abstract

PURPOSE:To attain the effective application of a main memory by recording the satisfaction or dissatisfaction of branch to the lower two bits of a branch address part of a branch instruction and observing the execution or non- execution of the program executing step. CONSTITUTION:A branch process part 130 fetches the contents of a main memory 200 shown by an execution mode instruction address holding part 111 into a branch instruction holding part 131. Then a branch condition deciding part 132 checks whether the branch conditions of a branch instruction are satisfied or not. If so, one of two lower bits of a branch destination address part of the branch instruction held by the part 131 is set at logic '1'. Then the branch instruction is written back to an address of the memory 200 held by the part 111. If not, the other bit is set at logic '1' and the branch instruction is written back to the address of the memory 200. In such a way, only the branch instruction is observed and therefore the deterioration of the actual performance is reduced. Then the memory 200 is effectively used since the memory 200 records the branch instruction itself and requires no other recording area.

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to a program execution step observation method for a computer system in which branch destination addresses in branch instructions are limited to addresses that are multiples of four. [Prior Art] Conventionally, there is a method of measuring coverage as one method for evaluating programs. For this purpose, a table having an area corresponding to each step of the program is prepared in main memory, and the data is measured every time an instruction is executed. The corresponding area of this table was filled in. [Problems to be Solved by the Invention] The conventional program execution step observation method described above prepares a table in main memory that has an area corresponding to each step of the program, and reads the corresponding area of the table each time an instruction is executed. The actual performance of the computer system is greatly reduced due to the blackout, and in order to suppress the decline in actual performance, many dedicated circuits must be prepared.
Since the correspondence table is prepared on the main memory, there is a drawback that the utilization efficiency of the main memory is reduced. [Means for Solving the Problems] The first program execution step observation method of the present invention includes: an executing instruction address holding means for holding an address on main memory of an instruction currently being executed; If the branch instruction is a branch instruction, the branch instruction holding means holds the branch instruction; and if the branch condition of the branch instruction is satisfied, the lower two of the branch destination address field of the branch instruction held in the branch instruction holding means; branch establishment recording means for writing back the branch instruction to an address on the main memory held in the executing instruction address holding means after setting one bit of the bits to logic "1"; and branching of the branch instruction. If the condition is not satisfied, the other bits of the lower two bits of the branch destination address part of the branch instruction held in the branch instruction holding means used by the branch establishment recording means are set to logic "L". and branch completion recording means for writing back the branch instruction to the address on the main memory held in the executing instruction address holding means. The second program execution step observation method of the present invention includes a currently executed instruction address holding unit that retains an address on main memory of an instruction currently being executed, and a branch instruction if the currently executed instruction is a branch instruction. branch instruction holding means for holding the branch instruction; branch trace mode setting means for setting whether or not to perform branch tracing of the branch instruction; and branch trace mode setting means for setting whether or not to perform branch tracing of the branch instruction; If the trace is indicated, one bit of the lower two bits of the branch destination address part of the branch instruction held in the branch instruction holding means is set to logic "L", and branch establishment recording means for writing back the branch instruction to an address on the main memory held; and if the branch condition of the branch instruction is not satisfied and the branch trace mode setting means indicates branch tracing of the branch instruction; Among the lower two bits of the branch destination address part of the branch instruction held in the branch instruction holding means, other bits of the bit used by the branch establishment recording means are set to logic "1", and the execution instruction is set to logic "1". and branch failure recording means for writing back the branch instruction to the address on the main memory held in the address holding means.

[Operation] The establishment or failure of a branch is recorded in the lower two bits of the branch address field of a branch instruction, and the execution or non-execution of a program execution step can be observed, and a table having an area corresponding to each step of the program can be created. Since there is no need to prepare and fill in the main memory, there is little deterioration in the actual performance of the computer system.Therefore, there is no need for a dedicated circuit to suppress the deterioration in actual performance, and the execution is recorded in the branch instruction itself. Since the storage area is not occupied, the main memory can be used effectively. Furthermore, in the second program execution step observation method, whether or not to perform branch tracing of branch instructions is set in the branch tracing mode setting means, and branch tracing is not performed when branch tracing is not necessary. Deterioration can be prevented. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a computer system to which an embodiment of the program execution step observation method (claim 1) of the present invention is applied, and FIG. 2 is a branch diagram used in the computer system of FIG. 3 is a flowchart showing the processing of the branch taken record means 133 of FIG. 1, and FIG. 4 is a flowchart of the processing of the branch not taken record means 135 of FIG. 1. The logical device 100 and the main storage device 200 constitute a computer system. The logic device 100 includes an instruction decoder 110
, an arithmetic processing section 120, and a branch processing section 130. The instruction decoding unit 110 includes an executing instruction address holding unit 111 and an instruction fetching unit 112, and the arithmetic processing unit 120 includes an arithmetic unit 121 and an instruction address updating unit 122.
The branch processing unit 130 includes a branch instruction holding unit 1
31, branch condition determination section 132, branch establishment recording means 133
, instruction address changing unit 134, branch failure recording unit 13
5 and an instruction address adder 136. In addition, in this computer system, the branch destination address in a branch instruction is limited to a multiple of 4, and the program instruction format consists of an instruction code section 1, an auxiliary code section 2, and an address section 3, as shown in Figure 2. The instruction code section 1 indicates the presence or absence of a branch, the auxiliary code section 2 indicates the branch condition,
Address portions 3 each represent a branch destination address. Since the branch destination address is limited to a multiple of 4, the lower two bits of the address field 3 are normally "0". The main storage device 200 stores instructions and data for programs to be executed from now on. The logic device 100 has a main memory 2 indicated by an executing instruction address holding unit 111 included in an instruction decoding unit 110.
00 is fetched to the instruction fetching unit 112, and the type of the instruction is checked. If it is a branch instruction, control is passed to the branch processing unit 130, and if it is other than a branch instruction, control is passed to the arithmetic processing unit 120. The instruction address updating unit 122 updates the address held in the currently executing instruction address holding unit 111 by a value corresponding to the instruction length of the executed instruction. On the other hand, if it is a branch instruction, the branch processing unit 130 transfers 4 bytes of the contents of the main storage device 200 indicated by the currently executed instruction address holding unit 111 to the branch instruction holding unit 131.
Incorporate into. Thereafter, the branch condition determining unit 132 checks whether the branch condition of the branch instruction is satisfied. If the branch condition is satisfied, as shown in FIG.
recorded on 0. That is, the second lowest bit (bit 30) of the 4-byte (32-bit) branch instruction held in the branch instruction holding unit 131 is set to logic "L" (step 11), and then the address of the instruction being executed is Holding part 11
Step 12) to retrieve the address on the main memory 200 of the branch instruction held by ``1'', write back the branch instruction with bit 30 set to logic ``1'' on the main memory 200 (step 13), and then , instruction address change unit 134
As a result, the lower two bits of the 20 bits of the branch destination address held by the branch instruction holding unit 131 are set to “00” and set in the currently executing instruction address holding unit 111. Also, if the branch condition is not satisfied, as shown in Figure 4,
The branch failure recording means 135 records on the main storage device 200 that the branch was not taken. That is,
The first bit (bit 3) from the lowest of the 4 bytes (32 bits) of branch instructions held in the branch instruction holding unit 131
Step 21) of setting 1) to logic "1", and then retrieving the address on the main storage device 200 of the branch instruction held by the currently executing instruction address holding unit 111 (step 22).
), the branch instruction with bit 31 set to logic "1" is written back onto the main memory 200 (step 23). After that, the instruction address adder 136 writes "4" corresponding to the instruction length of the branch instruction to the currently executed instruction address. It is added to the holding unit 111. Finally, the branch instruction written back to the main memory 200 is read and bits 30 and 31 of the address part are set to logic "".
1. Let the numbers of shouting objects be A and B, respectively.
If C is the total number of branch instructions, the coverage rate can be found by A+B. FIG. 5 is a block diagram of a computer system to which an embodiment of the program execution step observation method (claim 2) of the present invention is applied, and FIG. 6 is the processing of the branch establishment recording means 137 of FIG. FIG. 7 is a flowchart showing the processing of the branch failure recording means 138 in FIG. In this computer system, a branch trace mode setting section 113 is added to the instruction decoding section 110 of the logic device 100 in FIG. Branch recording means 133
Branch establishment recording means 137 with increased functions instead of
Further, in place of the branch failure record means 135, a branch failure record means 138 with increased functionality is provided. The logic device 100 fetches the contents on the main memory device 200 to the branch fetch unit 112, checks the type of instruction, and if it is a branch instruction, passes control to the branch processing unit 130, and if it is a branch trace mode setting instruction, the branch trace mode setting unit 113 is set to logic "1", and if it is not, the control is passed to the arithmetic processing unit 120. Here, if the instruction is other than a branch instruction or a branch trace mode setting instruction, the arithmetic processing unit 12 in the arithmetic processing unit 120
1, and the instruction address updating unit 122 updates the address held in the currently executing instruction address holding unit 111 by a value corresponding to the instruction length of the executed instruction. On the other hand, if the given instruction is a branch instruction, as in the embodiment shown in FIG. Then, branch condition judgment unit 1
32, it is checked whether the branch condition of the branch instruction is satisfied, and if the branch condition is satisfied and logic "1" is set in the branch trace monitor setting section 113, a branch establishment record is made as shown in FIG. The means 137 records on the main storage device 200 that the branch has been taken. That is, it is determined whether the branch trace mode setting section 113 is "1" (step 31), and if it is "l", it is the branch trace mode, so the branch instruction holding section 131 holds the value 4.
Set the second bit from the lowest (bit 30) of the byte (32 bits) branch instruction to logic “1” (Step 32)
Next, step 33) fetches the address on the main memory 200 of the branch instruction held by the executing instruction address holding unit 111. (step 34),
Thereafter, the instruction address changing unit 134 changes the contents of the currently executing instruction address holding unit 111 by regarding the lower two bits of the 20 bits of the branch destination address held by the branch instruction holding unit 131 as “OO”. Further, if the branch condition is not taken and the logic "l" is set in the branch trace mode setting unit 113, the branch not taken recording means 138 indicates that the branch was not taken, as shown in FIG. 200. That is, it is determined whether the branch trace mode setting section 113 is "1" (step 41), and if it is "1", it is the branch trace mode, so the 4-byte (32-bit) branch instruction held in the branch instruction holding section 131 is The first bit from the lowest (bit 31) is set to logic "1" (step 42), and then the address on the main storage device 200 of the branch instruction held in the currently executing instruction address holding unit 111 is retrieved. Step 43) Write back the branch instruction with bit 31 set to logic "L" onto main memory 200 (Step 4
4) After that, the instruction address addition unit 136 adds “4” corresponding to the instruction length of the branch instruction to the currently executed instruction address holding unit Ill. After this, the branch trace mode setting unit 113 is set to logic “1”.
is set, the coverage rate is measured by referring to the main storage device 200, as in the case of the computer system shown in FIG.

【Effect of the invention】

As explained above, in the present invention, when the branch condition of the branch instruction currently being executed is satisfied, one bit of the lower two bits of the branch destination address field of the branch instruction held in the branch instruction holding means is is set to logic "1" and the branch instruction is written back to the address on the main memory held in the executing instruction address holding means, and if the branch condition of the branch instruction is not satisfied, the branch instruction held in the branch instruction holding means is written back. By setting the other bits of the lower two bits of the branch destination address part of the branch instruction in the main memory to logic "1" and writing the branch instruction back to the address in the main memory, the main memory is stored for program step observation. Instead of preparing a correspondence table for each step of the program and filling it in, only the branch instructions are observed, so there is less deterioration in actual performance, and it can be realized with less dedicated circuitry. Since it does not require a recording area of This has the effect of further reducing deterioration in actual performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system to which an embodiment of the program execution step observation method (claim 1) of the present invention is applied, and FIG. 2 is a block diagram of the computer system of FIGS. 1 and 5. 3 is a flow chart showing the processing of the branch taken record means 133 of FIG.
FIG. 5 is a block diagram of a computer system to which an embodiment of the program execution step observation method (claim 2) of the present invention is applied, and FIG. 6 is a flowchart showing the processing of step 35. FIG. 7 is a flowchart showing the processing of the branch taken recorder 137, and FIG. 7 is a flowchart showing the processing of the branch not taken recorder 138 of FIG. l......Instruction code part, 2...
...condition part, 3...branch destination address part,
11, 12.13.21.22.23.31.32.3
3.34.41.42.43.44・・・・・・・・・
...Step, 100......Logical device, ■0...
・Instruction decoding unit, Ill......In-execution instruction address holding unit, 112...
Instruction fetching section, +13......Branch trace mode setting section, 20...... Arithmetic processing section, 21...... Arithmetic section, 22........Instruction address update section, 3
0......Branch processing section, 31...
...Branch instruction holding unit, 32...
...Branch condition judgment unit, 33, 137...
Branch taken record means, 34... Instruction address change unit, 35, 138... Branch not taken record means, 36... Instruction address adder, 200... Main memory.

Claims (1)

[Claims] 1. In a computer system in which a branch destination address in a branch instruction is limited to a multiple of 4, currently executing instruction address holding means for holding an address in main memory of an instruction currently being executed; A branch instruction holding unit that holds the branch instruction if the instruction being executed is a branch instruction, and a branch destination of the branch instruction held in the branch instruction holding unit if the branch condition of the branch instruction is satisfied. branch establishment recording means that writes back the branch instruction to the address on the main memory held in the executing instruction address holding means after setting one bit of the lower two bits of the address field to logic "1"; If the branch condition of the branch instruction is not satisfied, the other bits of the lower two bits of the branch destination address field of the branch instruction held in the branch instruction holding means are used by the branch establishment recording means. A program execution step observation system comprising: a branch execution recording means for writing back the branch instruction to the address on the main memory held in the executing instruction address holding means after setting the logic to "1". 2. In a computer system in which the branch destination address of a branch instruction is limited to a multiple of 4, an executing instruction address holding means that holds the address in main memory of the currently executing instruction, and a branch destination address of the currently executing instruction is branch instruction holding means for holding the branch instruction if it is an instruction; branch trace mode setting means for setting whether to perform branch tracing of the branch instruction; and branch trace mode setting means for setting whether or not to perform branch tracing of the branch instruction; If the mode setting means indicates a branch trace of the branch instruction, set one bit of the lower two bits of the branch destination address part of the branch instruction held in the branch instruction holding means to logic "1";
branch establishment recording means for writing back the branch instruction to an address on the main memory held in the executing instruction address holding means; and when the branch condition of the branch instruction is not satisfied, the branch trace mode setting means executes the branch execution of the branch instruction. If the trace is indicated, the other bits of the lower two bits of the branch destination address field of the branch instruction held in the branch instruction holding means used by the branch establishment recording means are set to logic "1'' and a branch failure recording means for writing back the branch instruction to the address on the main memory held in the executing instruction address holding means.