JPH05265799A - Data processor - Google Patents

Abstract

PURPOSE:To read/write data without update of the state of a cache memory especially for hardware debugging with respect to the data processor having the cache memory. CONSTITUTION:The data processor provided with an instruction executing means 1, a main storage 4, a cache memory 2 where data of the main storage is partially held, and a cache control means 3 for control of the cache memory 2 is provided with a cache data substituting means 3-1 and a stop means which stops the operation of this means 3-1, and the stop of the operating state of the cache data substituting means 3-1 is controlled by this stop means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a cache memory, and more particularly to a data processing device capable of reading and writing data without updating the cache state for hardware debugging.

[0002]

2. Description of the Related Art In a data processor, instead of directly accessing a memory, a high speed cache memory is prepared and first accessed, and if necessary data is present in the cache memory, it is used, and when it is not present, In other words, when there is no hit, the required data is transferred from the memory to the cache memory and accessed.

[0003]

By the way, debugging is performed in order to confirm whether or not the data processing device operates correctly. In the data processing device having the conventional cache device, since the cache automatically performs the data caching as described below, it is difficult to guarantee the reproducibility of the cache operation, and it is difficult to debug the hardware. is there.

That is, in the cache, when writing data, LRU management is performed, the latest accessed order is retained, and when the data is read from the memory and stored in the cache, the data that has not been accessed most recently is expelled. I am rewriting this. Therefore, when the cache memory is accessed, its LRU state changes. Therefore, when hardware debugging executes a print instruction to access the cache memory, for example, the LRU is updated. Even if the cache memory is to be returned to the pre-debug state after the end, the management data of the LRU and the contents of the cache memory have been changed and cannot be returned to the pre-debug state.

In particular, when the cache device is debugged, for example, in the case of hardware debugging in which the data replacement algorithm of the cache is wrong, the state of the cache data is changed by inserting an instruction for debugging. Therefore, reproducibility of execution cannot be guaranteed by debugging.

Further, in a cache device having a mechanism capable of explicitly controlling cache replacement by software, by executing a debugging instruction, a situation that can be assumed when the original instruction is executed can be assumed. Sometimes it goes wrong, so it makes a wrong run.

In such a situation, when an error caused by hardware or software occurs, it is difficult to reproduce the situation, and it is difficult to debug the program. Therefore, it is difficult to debug the hardware.
At the same time, software development was difficult.

However, in a system using a parallel cache and a data processing system having an instruction capable of controlling purging of the cache contents by an instruction, it is possible to inspect the data held in the cache during program execution. Great for debugging.

In such a case, conventionally, the execution is traced by a single clock operation or the like prepared in hardware, the problem of the hardware and the software is separated, and the debugging is performed. In addition to the program development, the software for the management system for performing the hardware management is required, which makes the development difficult and the man-hours for debugging increase.

Further, generally, in order to prevent the circuit scale from increasing, only a minimum amount of debugging hardware is prepared. Therefore, it is necessary to check the contents of the memory or rewrite the value. It often takes a lot of time.

[0011]

In order to solve the above problems, the present invention is configured so that the cache state, that is, the rewriting of data in the cache register and the LRU control can be stopped.

That is, as shown in FIG. 1, when the instruction execution unit 1 executes an instruction, the data in the main memory 4 is transferred to the cache memory 2 and the cache memory 2 is accessed to perform data processing. In addition to the above configuration, a cache data replacement permission flag (hereinafter referred to as a flag) 5 is provided, and the cache control unit 3 stops the rewriting of data in the cache memory 2 in response to "1" or "0" of the flag 5. Is.

For example, when the flag 5 is "1", rewriting of the cache memory 2 is stopped, and when the flag 5 is "0", rewriting is enabled. “1” and “0” of the flag 5 are directly entered by the instruction execution unit 1.

[0014]

Now, when the flag 5 is "1", the instruction execution unit 1
Issue a read command, the cache control unit 3 recognizes that it exists in the cache memory 2, accesses it, and sends out the desired data to the instruction execution unit 1, without changing the LRU control of the cache memory 2. , The flag 5 is stopped before it becomes "1".

If the read-destination data does not exist in the cache memory 2, the cache control unit 3 fetches this data from the main memory 4 and stores 1 in the reserved area of the cache memory 2.
Hold it temporarily and send the desired data to the instruction execution unit 1,
The reserved data is returned to the main memory 4. At this time L
The RU control is stopped.

In the case of a write command, the cache control unit 3 reads data from the main memory 4, temporarily holds it in the reserved area of the cache memory 2 and then writes it, and immediately returns it to the main memory 4.

By doing so, debugging can be performed without changing the cache state, so that the instruction executing section 1 may set the flag 5 to "1" during debugging.

Further, the instruction execution unit 1 may set the flag 5 to "0" when performing normal data processing. In this case, normal control is performed to rewrite the cache memory 2 or continue the LRU control.

Of course, it is also possible to stop the cache control when the flag 5 is "0".

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.
In the figure, the same symbols as in FIG. 1 indicate the same parts.

The instruction execution unit 1 executes a data processing operation, outputs a read instruction and a write instruction to the main memory 4, and sets a flag 5 to "1" or "0". is there. The cache memory 2 holds a part of the data in the main memory 4, and has a 1-way cache (direct map) column 2-0 and a reserve column 2-1. In the example of FIG. 2, the cache memory 2
Is a 1-way cache, but a multi-way configuration such as 4 WAY can also be used.

The cache control unit 3 performs cache control for the access request of the instruction execution unit 1,
It is detected whether or not the data written in the read command and the write command exists in the cache memory 2, and if it exists, the access based on this is performed, and if it does not exist, the desired data is read from the main memory 4. Column 2 of the cache memory 2 for the cache data replacement control unit 3-1
Control to replace the data written in 0.

The main memory 4 is a main memory of the data processing device and holds data necessary for the instruction executing section 1 to perform an operation. The flag 5 sets the mode in accordance with the "1" or "0". When the flag is "1", it is the cache control stop mode and is used during debugging. When it is "0", it is the normal mode. Is.

Now, when executing the program for debugging, the instruction execution section 1 sets the flag 5 to "1".
As a result, the cache control unit 3 stops the normal cache control function, the cache data replacement control unit 3-1 stops its operation, and replaces or rewrites the data in the column 2-0, which is the cache area of the cache memory 2. Or when performing LRU management, the LRU management is stopped.

When the instruction execution unit 1 issues a read instruction when the flag 5 is "1", if the cache control unit 3 recognizes that the cache control unit 3 exists in the cache memory 2, the cache control unit 3 accesses it to obtain necessary data. It is sent to the instruction execution unit 1.
If it does not exist in the cache memory 2, the cache control unit 3 reads the data block containing the desired data from the main memory 4, sets this in the column 2-1 of the reserve area of the cache memory 2, and stores it as necessary. The data is read and sent to the instruction execution unit 1. Then, the data set in the column 2-1 is returned to the main memory 4.

If the instruction execution unit 1 issues a write instruction,
The cache control unit 3 reads a data block containing Y data from the main memory 4, sets it in the column 2-1, writes it, and returns it to the main memory 4. However, if this data exists in the entangled 2-0 of the cache memory 2, it is rewritten.

It should be noted that the cache memory 2 is not provided with a reserve column, but a data holding means is provided in the cache control unit 3 to receive a data block read from the main memory 4 when the flag 5 is "1". The same processing as described above can also be performed.

When the flag 5 is "0", normal operation including cache data replacement control is performed. A second embodiment of the present invention will be described with reference to FIG. In FIG. 3, the flag 5 in FIG. 2 is not provided, and a normal cache operation is performed by an instruction, or cache data replacement is stopped.

In the second embodiment, when the cache replacement is stopped, as shown in FIG. 3B, a read instruction is formed as in and a write instruction is formed as in. Here, it indicates that the data at the address “0100” is read and written in the register ro, and is at the address “0100”.
It indicates that the data of the register ro is written in. In either case, you can stop doing cache replacements,
A symbol noruru indicating that the LRU control is stopped is added.

Note that, in FIG. 3B, a normal read instruction and a write instruction are shown. Indicates that the data of the address “0100” is read and written in the register ro, and indicates that the data of the register ro is written in the address “0100”.

In the second embodiment of the present invention, as shown in FIG. 3A, the cache control unit 3 is provided with an identification unit 3-0, and the instruction transmitted from the instruction execution unit 1 is a cache stop type or a normal type. To identify.

In the example of FIG. 3A, the cache memory 2
Indicates that the cache area is 4WAY in columns 2-0 to 2-3
In the configuration, columns 2-4 are reserved areas. Now, when the instruction execution unit 1 executes a program for debugging, if the instruction in the format of FIG. 3B is issued, the identification unit 3-0 in the cache control unit 3 decodes this and the cache is stopped. The cache data replacement control unit 3
Stop -1.

The data to be read is cache 2
If it is present, it is read and sent to the instruction execution unit 1. At this time, since the cache data replacement control unit 3-1 is stopped, the LRU control for returning to this access is not performed. Therefore, the access order of the LRU written in the tag 3-2 is the state before the stop. ,does not change.

If the data to be read does not exist in the cache 2, the cache controller 3 reads the required data block from the main memory 4 and sets it in column 2-4 of the reserve area of the cache memory 2. Then
The necessary data is sent to the instruction execution unit 1. Then, the data blocks set in the columns 2-4 are returned to the main memory 4.

If the instruction execution section 1 issues an instruction of the format shown in FIG. 3B, the identification section 3 of the cache control section 3 will be described.
-0 decodes this, and the cache data replacement control unit 3
-1 is stopped, the data block is read from the main memory 4, and the column 2 of the reserve area of the cache memory 2 is read.
-4 is set, and after necessary rewriting, this is returned to the main memory 4. In this case, if the access destination data exists in the cache memory 2, it will be rewritten.

If the instruction execution unit 1 issues an instruction of the format shown in FIG. 3B in the normal operation, the cache data replacement control unit 3-1 will execute the normal cache including the LRU control. Perform data replacement control.

Further, instead of the reserved area of the cache memory, data holding means may be provided for cache control.

[0038]

As described above, according to the present invention, the replacement control of cache data can be stopped, so that it can be stopped, for example, at the time of debugging and can be continuously operated in the state up to that point immediately after the end of debugging. Even if the program for debugging is executed in this manner, the same cache operation as when the program for debugging is not executed can be performed except for some cases.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1 instruction execution unit 2 cache memory 3 cache control unit 4 main memory 5 cache data replacement permission flag

Claims (3)

[Claims] 1. A data processing device comprising an instruction executing means, a main memory, a cache memory for holding a part of the data in the main memory, and a cache control means for controlling the cache memory. 1) and stop means for stopping the operation of the cache data replacement means (3-1), and the cache data replacement means (3-
A data processing device characterized in that the operation state of 1) is stopped and controlled. 2. The data processing apparatus according to claim 1, wherein a cache data replacement permission flag is provided as the stopping means. 3. The instruction identifying means (3-
0) is provided, and the operation state of the cache data replacing means (3-1) is stopped and controlled when the instruction transmitted from the instruction executing means (1) is specific. ..