JP2011192012A - Data processing system and access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To access data inside a memory at a high speed using a data structure including a pointer. <P>SOLUTION: In a computer system including the memory provided with a structure area for storing a plurality of structures and a data area for storing data, each structure includes a pointer for specifying the data stored in the data area, a data cache area for temporarily holding the data which are present in the data area and accessed once using the pointer, a flag for indicating that the data held in the data cache area are valid, and a counter value for holding the value of a counter register each time the value of the counter register is updated. When accessing the data inside the memory, the contents of the counter register and the counter value of the structure are verified, and the data inside the data cache area inside the structure or inside the data area specified by the pointer are accessed according to the verification results. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data processing system and an access control method, and more particularly to control for accessing a memory using a data structure (hereinafter simply referred to as a structure) in a data processing system having a data processor and a memory.

  In recent years, not only in the computer field, but also in electronic devices using embedded microcomputers, software development using high-level languages such as C language is generally performed. In software development using a high-level language, the use of structures and pointers is important for improving development efficiency and quality.

  For example, consider a case where a data structure using a structure and a pointer exists in a memory as shown in FIG. Since a pointer variable exists as a member in the structure, several memory addresses pointed to by the pointer are processed, and finally the actual data is reached. In this case, in order to access the actual data, the number of memory accesses corresponding to the number of stages of the pointer is required after accessing the structure. Therefore, it takes a long time to access the actual data, and this may cause a problem of performance degradation.

One way to solve this problem is to provide a hardware cache that can be accessed at high speed by the data user, but there is a problem that the hardware cost is high.
As an example of a memory structure using a pointer, one disclosed in Patent Document 1 is known, and as an example of a data cache, one disclosed in Patent Document 1 is known.

JP 2003-256267 A JP 2001-43130 A

As described above, the data structure using the pointer requires a plurality of memory accesses in order to access the data. Therefore, it takes a lot of time and the performance of the computer system is deteriorated.
Therefore, an object of the present invention is to access data in a memory at high speed in a data processing system using a data structure.

The computer system according to the present invention is preferably a computer system that can access data in a storage unit using a pointer held by a structure.
The storage unit includes a structure area that stores a plurality of the structures and a data area that stores data.
A counter register whose value is updated when certain data in the data area pointed to by the pointer is changed;
A pointer that specifies data stored in the data area, a data cache area that temporarily holds data in the data area accessed using the pointer, and a counter register value that is updated each time the value of the counter register is updated Comprising the structure having a counter value holding a value of a counter register;
When accessing the data in the storage unit, the contents of the counter register and the counter value of the structure are collated, and specified by the data cache area or the pointer in the structure according to the result of the collation The data processing system is characterized by accessing data in the data area.

In a preferred example, when accessing the data in the storage unit, the contents of the counter register are compared with the counter value of the structure. The data stored in the data cache area is used, and if there is a mismatch, the data in the data area specified by the pointer is used.
Preferably, when the data in the data area is accessed using the pointer, the acquired data is stored in the data cache area, and the value of the counter register is stored in the counter value of the structure. To do.
Preferably, the structure has a flag indicating that the data held in the data cache area is valid or invalid, and the data area specified by the pointer is changed when the data area is changed. Set the flag to an invalid state.
Preferably, when the number of entries in the structure area in which a plurality of the structures are stored is larger than the maximum value represented by the counter register, all the entries are deleted before the counter register makes one round. In order to invalidate, the flag of a certain plurality of structures is set to an invalid state.

In a preferred example, the computer system includes a network card connected to a network, a CPU for processing data, and a main memory having the structure area and the data area.
The structure holds control information corresponding to each of a plurality of transmission partners,
The counter register is provided in the network card;
The data area stores path information for each transmission partner, and the data cache area holds the path information in the data area designated by the pointer,
When transmitting data to a transmission partner, the network card reads the structure of control information for the transmission partner from the structure area in the main memory by DMA transfer, and further, the data cache area or the structure in the structure. Using the pointer, the path information is read from the data area by DMA transfer.

  In a preferred example, the external low-speed recording medium for storing data is connected, and the computer system has a CPU for processing data and a memory having the data area and the structure area, and the pointer is the external low-speed recording medium. The data stored in the recording medium is designated, and the data cache area holds the data stored in the external low-speed recording medium.

In the access control method according to the present invention, preferably, data in a storage unit having a structure area for storing a plurality of the structures and a data area for storing data is accessed using a pointer of the structure. An access control method that can
The structure has a pointer that specifies data stored in the data area, and a data cache area that temporarily holds data in the data area accessed using the pointer,
If the data stored in the data cache area of the structure is valid when accessing the storage unit, the data is obtained from the data cache area,
If the data stored in the data cache area of the structure is not valid, the access control method is configured to obtain data by accessing the data area using the pointer.

According to a preferred example, the access control method of the present invention accesses a data in a storage unit having a structure area for storing a plurality of the structures and a data area for storing data using a pointer of the structure. An access control method,
The structure includes a pointer for designating data stored in the data area, a data cache area for temporarily holding data in the data area accessed using the pointer, and a value of the counter register updated. A counter value that holds the value of the counter register each time
When accessing data in the storage unit, the contents of the counter register, whose value is updated when some data in the data area pointed to by the pointer is changed, are compared with the counter value of the structure; According to the result of the collation, the access control method is characterized in that the data in the data cache area in the structure or the data area specified by the pointer is accessed.

  According to the present invention, data in a memory can be accessed at high speed using a data structure having a pointer.

The figure which shows the data structure using a pointer. The figure which shows the structure of the data structure in one Example, its arrangement | sequence, and control of a cache. The figure which shows the cache invalidation at the time of the data update in one Example. The block diagram which shows the structure of the computer system by one Example. The figure which shows the example of the structure in one Example. The flowchart which shows the operation | movement at the time of the update of the route information by one Example. The flowchart which shows operation | movement in case the network card by one Example uses route information. The figure which shows the write-in operation | movement of the data in the computer system by one Example. The figure which shows the read-out operation | movement in the computer system by one Example.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 2 shows the structure of the data structure, its arrangement, and cache control.
In a storage unit such as a main memory in the computer system, a structure area 21 for storing a plurality of structures and a data area 22 for storing data to be accessed by a pointer of the structure are secured. The plurality of structures 210 are prepared for each transmission destination, for example.
Each structure 210 includes a pointer 211 indicating an address where data is stored, a data cache area 213 holding data in the accessed data area, a V bit 212 indicating that the cache data is valid, and a counter value 214. It has each field. Each structure 210 has the same fixed-length storage capacity such as 64 bytes. The storage capacity of the data cache area 213 is uniformly 16 bytes, for example.

First (first time), when data does not exist in the structure 210, the data of the address in the data area 22 designated by the pointer is acquired using the pointer 211 of the structure. The acquired data is stored in the field of the data cache area 213. As a result, the second and subsequent data accesses can be performed by reading the data from this field in the cache area 213 in the structure 210 without using the pointer.
The V bit 212 indicates whether the data in the data cache area 213 is valid. That is, when the actual data is stored in the data cache area 213, the V bit is set to “1”, and the contents of the data cache area 213 are invalidated because the actual data has been changed. The V bit is set to “0”.

A counter register 24 that can be accessed at high speed is prepared on the side that reads data in the structure, for example, a processor. The counter value 214 and the counter register 24 are necessary to maintain consistency between the value in the data cache area 213 in the structure and the data in the data area 22 corresponding to the memory address actually pointed to by the pointer 211. It is. Therefore, a comparator 25 that compares the counter value 214 with the contents of the counter register 24 is used. The comparator 25 may be configured by hardware or prepared by software.
When actual data existing at the memory address pointed to by the pointer is changed, the value of the data cache 213 in the structure 210 becomes an old value, and the data cannot be used. Therefore, the V bit 212 in the structure is set to “0” to invalidate the contents of the data cache 213.

Next, control for maintaining consistency between data in the data area 22 and data in the data cache area 213 and invalidation control for the V bit 212 will be described.
The invalidation control of the V bit 212 is performed by rewriting all the V bits 212 that are elements of all the structures 210 to “0” when a large number of structures 210 exist in the memory. Done. However, it takes time to write “0” to all the V bits, resulting in a decrease in the performance of the computer system. As a countermeasure, it is conceivable to rewrite the V bit of only the structure caching the actual data changed in the data area 22 to “0”, but it is necessary to carry out the pointers of all elements, and the number of stages of the pointers When there are many, it is not realistic.

  In the present embodiment, the counter value 214 is used to avoid performance degradation. The method will be described below. When the actual data present at the memory address pointed to by the pointer 211 is read and stored in the data cache area 213, the value of the counter register 24 is stored in the counter value 214 in the structure 210. When the actual data existing at the memory address in the data area 22 pointed to by the pointer is changed, the value of the counter register 24 is incremented. When the data in the data cache area 213 of the structure 21 is used, the counter value 214 in the structure and the value of the counter register 24 are compared by the comparator 25. If the two match as a result, the data cache area The data in the data cache is determined to be the latest, and the data in the data cache area is used.

  If they do not match as a result of the comparison, the data in the data cache area 213 is regarded as old, the latest data is read from the data area 22 using the pointer 211, and the data is used. Then, for the subsequent use of data, the latest data is stored in the data cache area 213, and the value of the counter register 24 at that time is stored in the counter value 214 in the structure. Thus, when the actual data existing at the memory address pointed to by the pointer is changed, it is not necessary to invalidate the data in the structure.

  However, when the number of data changes in the data area 22 is large, counter wrapping occurs, and the counter value 214 in the structure and the value of the counter register 24 become equal even though the data cache in the structure is old. There can be. For example, if the bit width of the counter is 5 bits, there are 32 counter values, so the count value of the 33rd round goes around to return to “0”, so it is “0” after going round the previous “0”. (Actually corresponds to 33), it becomes unclear and the invalidation control of the V bit is confused.

Therefore, control may be performed so that the data cache areas 213 in all the plurality of structures 210 are invalidated before the value of the counter register 24 goes around. That is, when the actual data is updated, the updated side controls the plurality of V bits to “0”.
For example, when the bit width of the counter register is 5 bits and the number of structure entries is 256, all entries are controlled to be invalidated when 32 counter values go around. As shown in FIG. 3, 256/32 = 8 entries are invalidated by one update. As a result, it is not necessary to rewrite the V bits of all structures to “0” in one update and invalidate the data in the data cache area, thereby preventing performance degradation.

With reference to FIG. 4, the memory access control of the structure in the computer system will be described.
The computer system 4 includes a CPU 41 for data processing, a main memory 42 connected to the CPU via a bus, and a network card 44 connected to the CPU via a chipset 43. The network card 44 is connected to the network 9. In the main memory 42, a plurality of structures 21 and data areas 22 are formed as shown in FIG. A counter register 45 is prepared as hardware in the controller LSI in the network card 44.
The dotted lines (arrows) in the figure represent the DMA write and DMA read routes. These pass through the CPU 41 as a route, but since a memory controller built in the CPU performs processing, instructions in the CPU are not hindered by DMA processing.

The structure 21 will be described with reference to FIG. Control information relating to a transmission partner when the network card 44 transmits to the network 9 is prepared as the structure 21. Usually, since there are a plurality of transmission partners, a structure for a plurality of entries is held corresponding to the transmission partners. The path information for each transmission partner is stored in the data area 22 of the main memory 42 managed separately from the structure holding the control information. The pointer 211 points to the address of the data area 22 where the path information is stored.
When transmitting data to a transmission partner, the network card 44 reads the control information structure 21 for the transmission partner from the main memory 42 by DMA transfer, and further uses the pointer 211 in the structure to perform main transfer by DMA transfer. It is necessary to read path information from the data area 22 of the memory 42. Here, path information is held in the data cache area 213 of the structure 21 so that the path information can be accessed at high speed when the control information structure is read. As a result, it is possible to reduce the time for reading the route information at the time of transmission, and to increase the speed of the transmission operation.

Next, a processing operation when the CPU 41 in the computer system of FIG. 5 changes the route information will be described with reference to FIG.
When the path information stored in the data area 22 of the main memory 42 is updated (S602), the counter register 45 in the network card 44 is incremented (S603). Next, the V bit in some structures 21 is set to “0” to invalidate the cache (S604). The invalidation control operation is as described above. Thereafter, the route information update process is terminated (S605).

Next, with reference to FIG. 7, a process when the network card uses route information will be described.
When the path information use process is started (S701), the control information structure 210 is read from the main memory 42 by DMA transfer (S702). Then, as a result of checking the V bit, if the V bit is “1” and the counter value 214 in the structure is compared with the value of the counter register 45 in the network card 44, the two values match. Data in the cache area 213 is regarded as the latest, and data (path information) in the data cache area is used (S704).

  On the other hand, if the V bit is not “1” and the result of the comparison is that they do not match, the data (path information) in the data cache area is not up-to-date, so the pointer 211 in the structure 210 is used. The data stored at the address of the data area 22 of the main memory 42 indicated by the pointer is read out by DMA transfer and used (S705). In this case, the latest path information is stored in the data cache area 213 in the structure 210, and at the same time, the value of the counter register 45 at that time is copied to the counter value 214 in the structure 210. At the same time, the V bit is set to “1” (S706). Thereafter, the used structure 210 is written back to the main memory 42 by DMA transfer (S707).

An example of data writing and reading in a data processing system using an external low-speed medium will be described with reference to FIGS.
Recently, the capacity of external low-speed media such as SD cards and optical drives has been increased, and not only OS (operating system) is put in HDD (hard disk drive) like before, but also OS is put in external low-speed media, It has been proposed to start from an external low-speed medium.

  For example, in a computer system in which a computer 80 such as a microprocessor having a CPU 81 and a memory (main memory) 82 and an external low-speed recording medium 88 are connected as shown in FIG. 821 is held. In this case, if the pointer in the low-speed storage medium is followed, the data exists in the same low-speed recording medium 88, and when accessing the data, the CPU 81 is much slower than accessing the memory 82. End up.

  The present invention provides a pointer, a cache area for storing data in the external low-speed medium 88, a V bit indicating validity / invalidity of data in the cache area, and a counter value indicating whether the data is the latest. By configuring as a structure and holding this structure in a part of the memory 82 in the computer 80, it is possible to speed up access to an external low-speed medium.

Hereinafter, data writing and reading operations will be described with reference to FIGS.
As shown in FIG. 8, when writing data, the CPU 81 writes data directly to the external low-speed medium (S801). At this time, the cache data in the memory 82 and the data in the external low-speed medium 88 are different, and the cache data of the pointer corresponding thereto is not correct data. Therefore, the cache data in the memory 82 must not be used. In such a case, the software counter 85 constituted by the CPU 81 and the memory 82 is incremented to indicate that it is not the latest cache (S802).
Since the software counter 85 overflows and wraps around, it may be determined that the latest data is not cached even though the latest data is not cached. Therefore, if the V bit of all entries of the structure is determined to be invalid before the software counter wraps around, the above case is eliminated. Thus, the V bit of the structure is invalidated by the maximum value + 1 of all entries / software counter (S803).

  Next, as shown in FIG. 9, the V bit is valid (is 1) in order to determine whether or not the data cached in the necessary pointer structure is the latest when reading the data corresponding to the pointer. In addition, the counter value in the structure and the value of the software counter 85 are compared to check whether they match (S804). If they match as a result of the check, it is determined that the latest correct data is cached in this structure, and the cached data is read (S805).

On the other hand, if the V bit of the structure is invalid (it is 0) or the counter value in the structure and the value of the software counter do not match, it is determined that the latest data is not in the structure, Following the pointer in the structure, data is read from the low-speed recording medium (S805 ').
Then, after reading data from the low-speed recording medium, the read data is cached and the same data is read next time. For this purpose, the read data is copied to the structure cache, and the software counter value is copied to the structure counter value. Then, the V bit is validated (S806 ′).

21, 210: Structure 22: Data area 211: Pointer
212: V bit 213: Data cache area 214: Counter value 24: Counter register 25: Comparator 4: Computer system 41: CPU 42: Main memory
43: Chipset 44: Network card 45: Counter register.

Claims (10)

In a computer system that can access data in a storage unit using a pointer of a structure,
The storage unit includes a structure area that stores a plurality of the structures and a data area that stores data.
A counter register whose value is updated when certain data in the data area pointed to by the pointer is changed;
A pointer that specifies data stored in the data area, a data cache area that temporarily holds data in the data area accessed using the pointer, and a counter register value that is updated each time the value of the counter register is updated Comprising the structure having a counter value holding a value of a counter register;
When accessing the data in the storage unit, the contents of the counter register and the counter value of the structure are collated, and specified by the data cache area or the pointer in the structure according to the result of the collation A data processing system for accessing data in a data area. When accessing the data in the storage unit, the contents of the counter register are compared with the counter value of the structure, and if the result of the comparison is that they match, the data cache area in the structure 2. The data processing system according to claim 1, wherein the stored data is used, and if there is a mismatch, the data in the data area specified by the pointer is used. When the data in the data area is accessed using the pointer, the acquired data is held in the data cache area, and the value of the counter register is stored in the counter value of the structure The data processing system according to any one of claims 1 to 2. The structure has a flag indicating that the data held in the data cache area is valid or invalid, and when the data in the data area designated by the pointer is changed, the flag is invalidated. The data processing system according to claim 1, wherein the data processing system is a data processing system. When the number of entries in the structure area in which a plurality of the structures are stored is larger than the maximum value represented by the counter register, all the entries are invalidated before the counter register makes a round. 5. The data processing system according to any one of claims 1 to 4, wherein the flag of a certain plurality of structures is set to an invalid state. The computer system includes a network card connected to a network, a CPU for data processing, and a main memory having the structure area and the data area,
The structure holds control information corresponding to each of a plurality of transmission partners,
The counter register is provided in the network card;
The data area stores path information for each transmission partner, and the data cache area holds the path information in the data area designated by the pointer,
When transmitting data to a transmission partner, the network card reads the structure of control information for the transmission partner from the structure area in the main memory by DMA transfer, and further, the data cache area or the structure in the structure. 6. The data processing system according to claim 1, wherein path information is read from the data area by DMA transfer using a pointer. A computer system connected to an external low-speed recording medium for storing data and having a data processing CPU and a memory having the data area and the structure area, wherein the pointer is stored in the external low-speed recording medium 6. The data processing system according to claim 1, wherein data is designated, and the data cache area holds data stored in the external low-speed recording medium. An access control method capable of accessing data in a storage unit having a structure area for storing a plurality of the structures and a data area for storing data using a pointer of the structure,
The structure has a pointer that specifies data stored in the data area, and a data cache area that temporarily holds data in the data area accessed using the pointer,
If the data stored in the data cache area of the structure is valid when accessing the storage unit, the data is obtained from the data cache area,
An access control method comprising: obtaining data by accessing the data area using the pointer if the data stored in the data cache area of the structure is not valid. An access control method for accessing data in a storage unit having a structure area for storing a plurality of the structures and a data area for storing data using a pointer of the structure,
The structure includes a pointer for designating data stored in the data area, a data cache area for temporarily holding data in the data area accessed using the pointer, and a value of the counter register updated. A counter value that holds the value of the counter register each time
When accessing data in the storage unit, the contents of the counter register, whose value is updated when some data in the data area pointed to by the pointer is changed, are compared with the counter value of the structure; An access control method comprising: accessing data in the data cache area or the data area designated by the pointer in the structure according to the result of the collation. The structure has a flag indicating that the data held in the data cache area is valid or invalid, and when the data in the data area designated by the pointer is changed, the flag is invalidated. 10. The access control method according to claim 8 or 9, wherein

Images