JPS603032A - Information processor - Google Patents

Abstract

PURPOSE:To store trace data which is effective at necessary sample timing in the investigation of the causes of trouble by employing a shift data memory as a trace memory. CONSTITUTION:The execution address of an instruction is stored in an instruction execution address register 1, and plural instruction addresses are set previously in an instruction address register 2. An address comparing circuit 3 compares the contents of the instruction execution address register 1 with those of the instruction address register 2. The shift data memory 4 is stored with shift data sent out through a shift path 52. A shift memory address register 5 indicates an address of the shift data memory 4. A main control circuit 6 selects one of plural instruction addresses to be compared next when the address comparing circuit 3 detects coincidence, and store shift data in the shift data memory 4 through a shift path together with the selected address to update the contents of the shift memory address register 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in the debugging function of an information processing bag ↑σ, and particularly to a method for controlling the trace timing of a tracer built into an information processing device.

(Prior Art) Conventionally, in information processing devices that have adopted the store program method, predetermined processing has been executed by repeatedly performing a series of operations such as reading an instruction, decoding the instruction, and executing the decoded instruction. . All of these operations involve transferring information between registers, shifting operations, using adders, etc.
It is executed by combining dozens of basic movements.

It is something that

Instructions that specify such basic operations are microinstructions, and a method of controlling the execution of each instruction by combining them is called a microprogram control method. The microbqgram was loaded into the memory, and the microinstructions were sequentially read out according to the address information input to the control memory 1 to proceed with the processing of each instruction.

, each instruction is generally realized by combining native microinstructions, but each instruction is implemented by an instruction counter (IC).
The instructions are executed sequentially according to the contents of an instruction execution address register called . In microprogram control type information processing devices, a method has been adopted in which a history of changes in the internal state of the information processing device is kept in a state history storage device and traced for debugging or other purposes.

However, there is a limit to the capacity of the storage unit used in the state history record system, and past trace data that exceeds the limit is rewritten and erased when new trace data is stored. That's why I put it away. In other words, in a microprogram control type information processing device, depending on the instruction, the waiting part, such as when the instruction execution address is used for the trace sample timing,
Or, the same operation may be repeated over a long period of time, causing trace data to overflow. In such a case, KU is the only state history record 1. There was a drawback that the storage section of the copying device H was full and the past portion useful for investigating the cause of the failure could not be sufficiently stored.

In addition, conventionally, in this type of information processing device ρ, it is not possible to leave the contents of the register in the storage section of the state history storage device, and it is not possible to store all the contents that are useful for investigating the cause of the failure. There was also a drawback. In other words, the internal world of the register file that is addressed at the trace timing is left as trace data even in conventional devices, but the contents of the register file that are not addressed at the trace timing are stored using a shift path. Therefore, in the conventional state history device, the above-mentioned contents could not be left as trace data.

jj, 'IM-, which is the cause of failure, i,', is a JQ in which the internal bounds of the register file of the address immediately before the address whose addressing has been zoomed out at the time of trace timing are valid.
: There are many i cases. Conventional equipment does not have a shift memory as a trace memory for collecting shift data using the -shift path, and therefore it is not possible to store the valid contents in such a case. There were also drawbacks.

(Object of the Invention) An object of the present invention is to improve an information processing device equipped with a conventional state history device arm, and to
A shift data memory is used as the trace memory that samples and extracts trace data and stores the shift data via a shift path only when an instruction specified by multiple instruction execution addresses is accessed. The object of the present invention is to solve the above-mentioned drawbacks and to provide a report processing device configured to be able to store valid trace data at the sample timing necessary for investigating the cause of a failure.

(Structure of the Invention) The information processing device according to the present invention performs 71° loading and reading of data including shift-based diagnosis/initialization, etc., and executes an instruction at the Il+T order according to the contents of an instruction execution address register that indicates the execution address of the instruction. , and is configured to include an instruction address register, an address comparison circuit, a shift data memory, a shift memory address register, and a main control circuit.

The instruction address register is used to preset the instruction address of (f). The address comparison circuit is used to compare the contents of the instruction execution address register and the contents of the instruction address register. The shift data memory is for storing shift data sent out through the shift path.The shift memory address register is for indicating the address of the shift data memory.

When the address comparison circuit detects a match output from the comparison result, the main control circuit selects one of the multiple instruction addresses to be compared next, stores the shift data in the shift data memory using the shift pass, and shifts This is used to control the operation of updating the contents of the memory address register.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a dimensional block diagram of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, 1 is an instruction execution address register, 2 is an instruction address register, 3 is an address comparison circuit, 4 is a shift data memory, 5 is a shift memory address register, 6 is a main control circuit, 7 is a comparison address register, 8 1 is an arithmetic operation control circuit, 9 is an address conversion circuit, 10 is the entire information processing device, 11 is a main storage device, 1
2 is a first increment circuit, 13 is a second increment circuit, and 14 is a maintenance/diagnosis device a.

In FIG. 1, an instruction execution address bus 1 is used to indicate the execution address of an instruction.

Two instruction address registers are configured so that a plurality of instruction execution addresses can be set in advance via the address bus 60. The address comparison circuit 3 is for comparing the contents of the instruction execution address 1/register 1 and the contents of the instruction address register 2. The address conversion circuit 9 is for converting the contents of the instruction execution address register 1 into a request address signal to the main storage device 11 and sending it onto the signal line 54.

The arithmetic control circuit 8 is controlled by instructions obtained from the main memory 11 via the data bus 53, and controls the main operations and the entire tray. The arithmetic control circuit 8 also generates the contents of the power instruction address register to be executed next. The shift data memory 4i is for storing shift data sent out via the shift path 52. Shift memory address register 5
1, the address of shift data memory 4 is specified +Z). % Mii
) A hold signal is sent onto the signal line 50 in response to the address match signal sent onto the address matching signal 56, and the operation of the arithmetic control circuit 8 is interrupted in a state where it can be restarted. [First increment circuit] In accordance with the shift control by the 2d1 main control circuit 6, the shift data is stored in the shift memory address register 5 via the shift path 52, and the at1/count up instruction is sent on the signal line 59. This signal is used to incrementally dry the contents of the shift memory address register 5. The address count up instruction signal on the second increment circuit 131-1 signal line 55 causes the instruction address register 2 to be compared next.
Address indicator Hiaki Rudame address register 7 (
This is the 1jth one that increments the address that is marked with C cents.

Shift data is stored in shift data memory 4 at t'6 beat fi
After the command is completed, Knee is added to Raku8 once in the σ control to instruct the start from the next command.
8- Fill the main line through the line 5
(Sent from 6-'1 circuit 6. Maintenance diagnosis method Hw 1
4 is an i-path 57 that stores the contents of the shift data memory 4 for debugging. Take it in and stop it!
This is for outputting one message to the lδζT control circuit 8 via the lδζT control circuit 8.

In this case, I
Nuttat signal +1 via id signal and 1?6]! −? It is something that is sent out.

At the beginning of the maintenance diagnosis-1g4 to 14, the stop 1417 Chengren-22- is sent out via the 18ze line 58, and the command-B line is sent to the arithmetic control circuit 8 in the idle state. Re;:11 Instruct to stop while possible. Next, the debug nabe nakamike's i+&instruction 3 line address is stored in the -r instruction address register 2 via the address bus 60. Then s 07 ++=, iil
The start instruction signal 61 instructs the arithmetic control circuit 8 to resume execution of instructions, and causes the debugging job to be executed. The initial value of the comparison address register 7 is set to 0 and is h-. The contents of the instruction address register 2 specified by this comparison address register 7 and the instruction execution address register indicating the execution address of the instruction]
Of these, 'IJ-' is compared by the address comparison circuit 3.

When the two match, the address match signal is on the signal line 56.
Occurs on the rise. The main side 01 circuit 6, which has been notified of the address match by the address match signal, uses the hold signal on the signal line 50 to keep the arithmetic control circuit 8 in a state where it can restart instruction execution and stops it. All shift data of the information processing device 1° is stored in the RAM.
It is stored in the shift data memory 4 including the contents of. At this time, the contents of shift memory address register 5 are also changed.
It is applied to the first increment circuit 12 via an address count up instruction signal on signal line 59. Therefore, the number of cheetah pits that should be stored is the same as the first one.
The contents of the increment circuit 12 are incremented by one. Here, the initial value of the shift memory address register 5 is 0.

Now, when all of the shift data has been stored in the shift data memory 4, the main control circuit 6 increments the contents of the instruction address register 2 by 1 via the address count up instruction signal on the signal line 55. The instruction is given to the increment 1/ment circuit 13, and then the contents of the comparison command address register are shown. Along with this, the main side false 1 circuit 6
A start signal on the signal line 51 instructs the arithmetic operation 1b control circuit 8 to restart instruction execution.

In this way, every time the contents of the instruction address register 2 and the contents of the meeting execution address register 1 indicating the execution address of the instruction match, the shift data of one blue report processing device IO is transferred to the shift data memory 4. It will be stored. When execution of a predetermined job is completed, or when the information processing device 10 is stalled or stopped due to a failure, the maintenance diagnostic device 14 instructs the arithmetic control circuit to stop via the stop instruction signal line 58. The contents of the shift data memory 4, which is a trace memory of 10 yen, are taken into the ear protection diagnostic device i1 "f" 14 via the data path 57.

(Effect of Koreaki) As explained above, Ichiki's invention has the advantage of sampling and extracting trace data only when an instruction specified by one of the seven instruction execution addresses specified in advance is accessed. However, by making it a point to use a shift data memory that can store shift data using a shift path as a trace memory, it is possible to store valid trace data at the required sample timing (in investigating the cause of a failure). There is an effect that says it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one implementation of an information processing apparatus according to the present invention. 1.2.5.7...Register 3...Ratio axis circuit 4...Memory 6...Main! 1tII control circuit 8...'IX arithmetic control circuit 9...Address conversion circuit lO...Information processing device 11...Prison f, hT decompression 12.13...Increment circuit 14...Maintenance Diagnostic device 50-6I...Signal line (passes through) Patent applicant Nippon'1 Koki Co., Ltd. Agent Ben Sokuji Noro ",'7

Claims (1)

[Claims] Data is written and read out, including the argument/initial setting, etc. through the shift path, and the instructions are executed sequentially according to the contents of the instruction execution address register, which specifies the execution position of the instruction. In the information processing facility),
1′! an instruction address register for setting the instruction address in advance, an address comparison circuit for comparing the contents of the instruction execution address register with the contents of the instruction address register, and shift data stored via the shift bus. a shift data memory to be executed; a shift memory address register for instructing the at 1/s of the shift data memory; and a shift memory address register for instructing the address of the shift data memory; and a main control circuit for controlling the #1 operation so as to select and measure one shift data and to update the contents of the Qft shift memory address register by storing the shift data in the ^11 shift data memory using the shift pass. An information processing device characterized in that it is configured as follows.