JPS5528536A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5528536A
JPS5528536A JP10074878A JP10074878A JPS5528536A JP S5528536 A JPS5528536 A JP S5528536A JP 10074878 A JP10074878 A JP 10074878A JP 10074878 A JP10074878 A JP 10074878A JP S5528536 A JPS5528536 A JP S5528536A
Authority
JP
Japan
Prior art keywords
signal
control signal
gate
featuring
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10074878A
Other languages
Japanese (ja)
Inventor
Yasuo Akatsuka
Shigeki Matsue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10074878A priority Critical patent/JPS5528536A/en
Publication of JPS5528536A publication Critical patent/JPS5528536A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To realize the writing free from the error caused by the noise by converting the write signal featuring the 2nd control signal into the 2nd write control signal featuring a shorter writing indication period. CONSTITUTION:Control signal terminal W' is provided to memory integrated circuit chip 10, and signal DW' sent via delay circuit D is supplied to NOR gate NG. The output of NOR gate NG is used for write control signal W of chip 10. Writing indication signal W' keeps the low level from period tA to tC; while signal DW' is delayed via circuit D and features the low level at and after time point tB. These signals are converted through NOR gate NG into signal W featuring the high level for a short period from tB through tC to be delivered. As signal W' features a longer period pulse than signal W to be memorized, the noise can be discriminated easily.
JP10074878A 1978-08-17 1978-08-17 Memory circuit Pending JPS5528536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10074878A JPS5528536A (en) 1978-08-17 1978-08-17 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10074878A JPS5528536A (en) 1978-08-17 1978-08-17 Memory circuit

Publications (1)

Publication Number Publication Date
JPS5528536A true JPS5528536A (en) 1980-02-29

Family

ID=14282147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10074878A Pending JPS5528536A (en) 1978-08-17 1978-08-17 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5528536A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57202065A (en) * 1981-06-05 1982-12-10 Hitachi Ltd Fuel cell
JPS59124089A (en) * 1982-12-29 1984-07-18 Fujitsu Ltd Semiconductor storage circuit
EP0158028A2 (en) * 1984-02-27 1985-10-16 Kabushiki Kaisha Toshiba Random access memory device
EP0273652A2 (en) * 1986-12-19 1988-07-06 Fujitsu Limited Pseudo-static memory device having internal self-refresh circuit
JPH0291892A (en) * 1988-09-27 1990-03-30 Nec Corp Memory circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5235535A (en) * 1975-09-12 1977-03-18 Hitachi Ltd Semiconductor memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5235535A (en) * 1975-09-12 1977-03-18 Hitachi Ltd Semiconductor memory

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57202065A (en) * 1981-06-05 1982-12-10 Hitachi Ltd Fuel cell
JPS6335070B2 (en) * 1981-06-05 1988-07-13 Hitachi Ltd
JPS59124089A (en) * 1982-12-29 1984-07-18 Fujitsu Ltd Semiconductor storage circuit
EP0158028A2 (en) * 1984-02-27 1985-10-16 Kabushiki Kaisha Toshiba Random access memory device
EP0273652A2 (en) * 1986-12-19 1988-07-06 Fujitsu Limited Pseudo-static memory device having internal self-refresh circuit
JPH0291892A (en) * 1988-09-27 1990-03-30 Nec Corp Memory circuit

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