JPS6115458B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a diagnostic method that, when diagnosing a system with a retry function, does not perform a retry operation even if an error is detected during execution of the diagnosis.

FIG. 1 explains the diagnosis of an input/output system, particularly a channel control device, and numeral 1 indicates a channel control device, 2 a channel, 3 a storage device, and 4 a diagnostic processing device. When diagnosing the channel control device 1, the diagnostic processing device 4 supplies the channel control device 1 with an operation designation signal and an operation clock number designation signal, and sends out a diagnosis activation signal to activate the channel control device 1. The channel control device 1 is
When started, it executes the specified process for the specified number of clocks, and after completing the process for the specified number of clocks,
The status information is logged out and stored in a fixed area of the storage device 3. The diagnostic processing device 4 reads the logout data, compares the logout data with the predicted data, and determines that there is an error if they do not match. By the way, if an error is detected in channel control device 1 or channel 2 during operation of the input/output system shown in FIG. 1, a retry is executed. Since the above prediction data is created on the premise of normal operation, if a retry is executed, the prediction data and the logout data after the occurrence will all be inconsistent.

It is also possible to create prediction data assuming retries, but the causes of retries, number of retries, and retry execution time vary widely.
Create predictive data assuming retries, log
It is impossible to match the out data.

The present invention is based on the above considerations, and includes:
The object of the present invention is to provide a diagnostic method that can continuously and correctly diagnose a system having a retry function. Therefore, the diagnostic method of the present invention includes a system or device to be diagnosed having a retry function, and a diagnostic processing device,
The diagnostic processing device sends operation designation information, a clock number, a diagnostic mode signal, and a diagnostic start signal to the system to be diagnosed or the device to be diagnosed, and the system to be diagnosed or the device to be diagnosed executes processing according to instructions from the diagnostic processing device. , and in a diagnostic method for logging out status information, means for generating an error ignore signal of a predetermined value when the diagnostic mode signal is received, and retrying even if an error occurs when the error ignore signal is at a predetermined value. The present invention is characterized by comprising means for executing a retry when an error that can be retried under a state where the error ignore signal is at another predetermined value without executing the error ignore signal is generated. Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of a channel control device used in the present invention, and FIG. 3 is a block diagram of one embodiment of a channel used in the present invention.
In FIGS. 2 and 3, 5 is a diagnostic data register, 6 is a clock counter, 7 is a log out circuit, 8 is a diagnostic start flip-flop, 9 is a diagnostic mode flip-flop, and 9a
9b is a gate that opens when the diagnostic mode flip-flop is set; 9b is a gate that closes when the diagnostic mode flip-flop is set;
10 is an OR circuit, 11 is an error check circuit, 1
2 is the memory store data register, 13 is the subchannel memory data register, 14 is the subchannel memory, 15 is the subchannel memory address register, 16 is the memory address register, KENEG is the error ignore signal by the switch. , 17 is an error check circuit, 18 is various error flip-flops, 19 is an access control circuit, 20 is an instruction decoder, 21 is a sequence control circuit, 22 is an IO interface control circuit, 23 is a status register, and 24 is a decoder.・Registers, 25 is an assemble/disassemble circuit, 26 is an IO buffer register, 27 is a channel command register, 28 is a data
address register, 29 is a channel address word register, 30 and 31 are AND circuits, 32 is an OR circuit, 33 and 34 are NOT circuits,
RE indicates a retryable error, and URE indicates a non-retryable error.

The gist of the present invention is that in the diagnostic mode, even if an error is detected, the error is ignored, thereby preventing a retry from being executed. below,
This point will be explained in detail.

It should be noted that most of the circuits shown in FIGS. 2 and 3 are conventional ones.

The diagnostic data register 5 contains the diagnostic processing device 4.
The diagnostic data sent from is set. The clock counter 6 is set with the number of clocks sent from the diagnostic processing device 4. The diagnostic mode flip-flop is set when the diagnostic mode signal goes to ``1''. When flip-flop 9 is set, gate 9a opens and gate 9b closes. When the diagnostic start signal becomes "1", the diagnostic start flip-flop 8 applies a system clock to the channel control device 1 and the channel 2, thereby bringing them into operation. The logout circuit 7 collects status information of the channel control device 1 when the content of the clock counter 6 becomes zero;
This is written in a fixed area of the storage device 3. Key-based error ignore signals also exist in the prior art. The ignore error signal from this key and the ignore error signal from flip-flop 9 are sent to channel 2. Error check circuit 1
1 detects an error within the channel control device 1, and if the error is related to a channel, it notifies the channel of the error occurrence and error type. The error check circuit 17 detects errors within the channel 2. error·
The flip-flop 18 is connected to the channel control device 1
and stores various errors occurring in channel 2. Among the errors stored in the error flip-flop 18, the non-retryable error URE is notified to the sequence control circuit 21, and the retryable error is notified to the access control circuit 19 via the AND circuit 30. Further, when no error is stored, the NOT circuit outputs a logic "1".
The logic “1” signal output from the NOT circuit 33 indicates no error, and this signal is also input to the sequence control circuit 21. When the error ignore signal is "1", the AND circuit 30 outputs logic "0". A logic "1" signal of the AND circuit 30 indicates that retry is possible, and a logic "0" signal indicates that retry is not possible. Also, if the error ignore signal is logic “1”,
Even if an error is stored in the error flip-flop 18, the AND circuit 31 outputs a logic "1", and this logic "1" signal is sent to the OR circuit 3.
2 to the access control circuit 19 and sequence control circuit 21 as a no-error signal. The access control circuit 19 accesses the storage device 3, subchannel memory 14, and the like. This access control circuit 19 repeats the same access when an error is notified during the access operation and the retry enable signal is logic "1".
When the sequence control circuit 21 is notified of no error, the sequence control circuit 21 advances the control to the next step, and when notified of the retry impossible error, it stops the control.

Next, diagnosis of the subchannel memory 14 will be described as a specific example. Diagnosis of the subchannel memory is performed by the diagnostic processing unit 4 using the diagnostic data register 5.
Set an instruction code to instruct that subchannel memory 14 should be accessed at
This is done by setting the specified clock length in counter 6, setting diagnostic mode flip-flop 9, and setting diagnostic start flip-flop 8. The instruction code in the diagnostic data register 5 is sent to the instruction decoder 2 via the gate 9a.
0 and is decoded by the instruction decoder 20. The sequence control circuit 21 advances control according to the decoding result of the instruction decoder 20. The address of subchannel memory 14 to be accessed is set in data address register 28;
This address information is set in subchannel memory address register 15 and subchannel memory 14 is accessed. Assuming that it is a read case, the read data from subchannel memory 14 is first set in subchannel memory register 13 and then set in data register 24 via the data bus. Note that the △ and ▲ marks in FIGS. 2 and 3 indicate that the bus will be checked for errors. Errors in read data are checked by an error check circuit 11 or 17. If the error ignore signal is a logic "0", channel 2 causes the access control circuit 19 to retry. However, since the error ignore signal is logic "1" in the diagnostic mode, retrying is suppressed. When processing has been performed for the specified number of clocks, channel control device 1 and channel 2 are stopped, and logout is performed by the logout circuit.

As is clear from the above description, according to the present invention, a diagnosed device or system having a retry function can always be correctly executed.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining diagnosis of the input/output system, particularly the channel control device, Fig. 2 is a block diagram of one embodiment of the channel control device used in the present invention, and Fig. 3 is a diagram showing the channel control device used in the present invention. FIG. 2 is a block diagram of one embodiment of the invention. DESCRIPTION OF SYMBOLS 1...Channel control device, 2...Channel, 3...Storage device, 4...Diagnostic processing device, 5...Diagnostic data register, 6...Clock counter, 7...Logout circuit, 8...Diagnostic start flip-flop, 9... Diagnostic mode flip-flop, 9a
...gate that opens when the diagnostic mode flip-flop is set; 9b...gate that closes when the diagnostic mode flip-flop is set;
10...OR circuit, 11...Error check circuit, 1
2...Memory store data register, 13...Subchannel memory data register, 14...
Subchannel memory, 15...Subchannel memory address register, 16...Memory address register, KENEG...Error ignore signal by switch, 17...Error check circuit, 18...
Various error flip-flops, 19...Access control circuit, 20...Instruction decoder, 21...Sequence control circuit, 22...IO interface control circuit, 23...Status register, 24...Data register, 25...Assemble/disassemble Circuit, 26...io buffer register, 27...
Channel command register, 28...data
Address register, 29...Channel address word register, 30 and 31...AND circuit, 32...OR circuit, 33 and 34...NOT circuit,
RE...Retryable error, URE...Retryable error.

Claims (1)

[Claims] 1. A system to be diagnosed or a device to be diagnosed that has a retry function and a diagnostic processing device are provided, and the diagnostic processing device sends operation designation information, the number of clocks, a diagnostic mode signal, and a diagnostic start signal to the system to be diagnosed or the device to be diagnosed. , in a diagnostic method in which the system to be diagnosed or the device to be diagnosed executes processing according to instructions from a diagnostic processing device and logs out status information, means for generating an error ignore signal of a predetermined value when receiving the diagnostic mode signal; and,
If the above error ignore signal is at a predetermined value, no retry will be performed even if an error occurs; if the above error ignore signal is at another predetermined value, a retry will be performed if a retryable error occurs. A diagnostic method characterized by comprising means for: