JPS58186853A - Initial diagnostic system - Google Patents

Abstract

PURPOSE:To facilitate an initial diagnosis while adding a little hardware, by providing an FF which is set in a diagnostic mode and reset by a microprogram, and a control circuit which alters a microprogram sequence according to the state of the FF. CONSTITUTION:A cash memory 102 is provided between a main memory 101 and an arithmetic control circuit 103 controlled by the microprogram stored in a control storage part 104 to constitute an information processor. This processor is provided with the FF106 which is set in diagnostic mode right after power-on operation and reset under the program control of the circuit 103. A sequence controller part 105 alters the sequence of the microprogram according to the state of the FF106. Then, the program is stored in the memory 103 and after processing is carried out according to the stored program, a check on whether the program processing is completed normal or not is made in an initial diagnostic routine by adding a little hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an initial diagnosis method used in an information processing apparatus having a high-speed buffer storage mechanism (cache memory).

[Technical background of the invention and its problems]

In recent years, with the advancement of semiconductor technology, semiconductor memory elements have become cheap and easily available, and even small computers such as minicomputers are equipped with cache memory to improve performance. This device configuration has become widespread. On the other hand, methods for controlling computers using microprograms have become common, and RAS (Reliab%11t
y, Avail-ability + 5ervi
Many of them have diagnostic functions using microprograms, with the aim of improving performance (e.g., eyesight).

At this time, in diagnosis using a microprogram, it is easy to diagnose the data bus system of the arithmetic circuit, but it is difficult to diagnose the control circuit for executing instructions.

Particularly in small electronic computers, it is difficult to add additional software for diagnosis due to cost considerations, and the current situation is that diagnostics other than data and motherboards are not normally performed.

[Object of the Invention] The present invention was developed in view of the above-mentioned circumstances, and it is an inexpensive and easy method to effectively use the existing software to control the command execution in the initial diagnosis using a microprogram when the power is turned on. The purpose is to provide an initial diagnosis method that can diagnose the disease.

[Summary of the invention]

In the present invention, when a flip-flop is set to indicate that an initial diagnosis is being performed immediately after power is turned on, the set signal of the flip-flop is used as a condition for determining the program sequence, and a microprogram sequence consisting of the set signal is written into the cache memory, and the program is followed. After the processing is executed, the processing operation is returned to the normal initial diagnosis routine under program control to check the validity of the processing results.

As a result, the instruction execution control circuit can be easily and effectively diagnosed using existing hardware.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the figure, 10 is volatile or non-volatile main memory (MM), 1
02 is a cache memory (CA) that serves as a high-speed buffer storage mechanism.
CHE). 103 is an arithmetic control circuit (CNT) for reading/writing the main memory 101 (and cache memory 102), and is a control section (C8) 7 which stores 104 microprograms. 105 controls the seek yx of the microprogram.
- sequence controller (5EQCNT). 106 is a pulse signal (hereinafter referred to as PU) generated when the power is turned on.
A flip-flop (PFF) signal is set by the P signal and reset upon completion of initialization.

Here, the operation of one embodiment will be explained. The main memory 101 reads/writes data in response to read/write requests from the arithmetic control circuit 103.

When the flip-flop 106 is in the reset state, this main memory 10 accepts requests from the arithmetic control circuit 103 unconditionally, but when the flip-flop 106 is in the set state, in the case of a nonvolatile memory structure, the arithmetic control circuit 103 accepts requests from the arithmetic control circuit 103. The request from circuit 103 is ignored. This function allows the microprogram to run the memory initialization routine without knowing the type of memory when the microprogram initializes the volatile memory (normally by writing 0" to all addresses) when the power is turned on. The cache memory 102 is a buffer memory located between the main memory 10 and the arithmetic control circuit 103, and the arithmetic control circuit 103 is located between the main memory 101 and the arithmetic control circuit 103.
When reading data from , based on a certain method,
5- Hold that data temporarily. Thereafter, when the arithmetic control circuit 1θ3 reads data that is also held in the cache memory 102 from the main memory 10, the data is read from the cache memory 102 instead of from the main memory 101. On the other hand, when the arithmetic control circuit ios replaces data held also in the cache memory 102 by a write operation, the data held in the cache memory 102 and the main memory IJ J 01
Both data will be rewritten. Arithmetic control circuit 103
By the read access operation to the main memory 101, the data held in the cache memory 102 is exchanged one after another according to a predetermined method. . The arithmetic control circuit 103 performs various controls such as execution of arithmetic operations based on data (microinstructions) serially read by the control store section 104. Control “Store unit 104, according to the address information from the td sequence controller 105,
A 6-control memory is used to output a microinstruction corresponding to the address, and stores a microprogram. Sequence core) roller 105 is arithmetic control circuit 103
, and the sequence of the microprogram based on the signals from the flip-flop 106. The flip-flop 106 is a flip-flop that indicates that the power is turned on. It is set by the PUP signal generated when the power is turned on, and when various processes are executed by a microprogram at the time of power-on, the last microinstruction is used. will be reset.

Next, the diagnosis of instruction execution operations by initial microprogram diagnosis will be explained. The initial diagnosis is performed when the power is turned on, that is, while the flip-flop 106 is set. First, as a preprocessing when writing a microzologram sequence that requires a control operation check to the cache memory 102, the contents of the area of the main memory 101 are also held in the cache memory 1θ2. Although this method depends on the cache system, it can be easily implemented by reading the main memory using an appropriate method.

Next, the microprogram performs a write operation to the main memory 101 and writes the two-instruction sequence in the cache memory 102. This write operation is performed when the main memory 10 has a non-volatile memory structure, and the cache memory 1
A write operation is performed only to 02, so that the contents of the main memory 101 are not damaged due to diagnosis.

In addition, in the case of a volatile memory structure, a write operation is also performed to the main memory 101, but after the initial diagnosis, the main memory l
Since the initialization process for θ1 is performed, no inconvenience occurs. The last instruction sequence written to the cache memory 102 is an IJ-gal instruction. Next, the microprogram starts controlling the execution of instructions from the first address of the instruction sequence. Here, the microprogram sequence departs from the routine for initial diagnosis and enters a normal instruction execution routine. The arithmetic control circuit 103 sequentially processes the instructions, and when the last instruction is executed, an illegal instruction is detected and control is transferred to an illegal instruction processing routine. The illegal instruction processing routine normally generates an interrupt to notify the software of the occurrence of an illegal instruction. At this time, the routine checks the state of the flip-flop 106 and
When 06 is in the set state, it is determined that diagnosis is in progress and the microprogram sequence is returned to the initial diagnosis routine. When control is returned, the initial diagnostic routine checks the result of command execution and performs a diagnosis. Note that if the main memory 101 has a non-volatile memory structure, at this point the main memory 101 and the cache memory 10
Although there is a discrepancy between the contents of 2 and 2, no inconvenience occurs because the cache memory 102 is initialized during power-on processing performed after diagnosis.

This type of initial diagnostic processing operation eliminates the need for complex hardware and air conditioning that is unique to diagnosing the operation of the control circuit for instruction execution, and allows the operation of the control circuit for instruction execution to be performed in addition to existing diagnostics when the power is turned on. This allows a reliable initial diagnosis to be made.

In the above embodiment, the last of the instruction sequence is an illegal instruction, and the process returns to the microprogram routine for processing the illegal instruction, and then returns to the diagnostic routine depending on the set state of the flip-flop 106. However, other methods may also be used. Any method that can return to the diagnostic routine by referring to the 7'70 Tsude 106 may be used. Further, although the flip-flop 106 provided for memory clearing when the power is turned on is used, a separate flip-flop (flag register) Kff indicating that diagnosis is in progress may be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to diagnose the instruction execution control circuit at low cost and easily by effectively using existing hardware at the time of initial shutdown due to the microb "J-gram" when the power is turned on. − It can provide an initial diagnosis method that allows for

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 101... Main memory (MM), J(M'... CACHE), 1θ3... Arithmetic control circuit (CNT), 104... Control store section (C
8), 105... Sequence controller (5EQC
NT), 106... Frizzo Frodde (PFF)
. Applicant's agent Patent attorney Takehiko Suzue 11-

Claims (1)

[Claims] In an information processing device in which a cache memory is interposed between an arithmetic control circuit controlled by a microprogram and the main memory, it is set in the diagnostic mode immediately after power is turned on, and is reset by the microprogram control. a flip-flop; a sequence control circuit that changes a microprogram sequence according to the state of the flip-flop; and a sequence control circuit that stores a program in the cache memory when the flip-flop is in a set state under the control of the sequence control circuit; 1. An initial diagnosis method, comprising means for executing processing according to a program stored in a memory, and checking the validity of the program processing in an initial diagnosis routine after the processing of the program is executed.