JPH07225734A - Method for monitoring decoder for selection to select peripheral device of central processing unit and information processor for the same - Google Patents

Abstract

PURPOSE:To facilitate fault analysis by more narrowly limiting and detecting the defective part of a hardware by monitoring a device for decoding the peripheral device of a central processing unit (CPU). CONSTITUTION:This method is composed of a CPU 1 provided with an address bus 8 and a data bus 9, peripheral devices 2-4 of the CPU 1 connected to the buses 8 and 9, decoder 5 for decoding the address data of the address bus 8 and outputting a select signal to select any one of peripheral devices 2-4, and monitoring register 6 for temporarily recording and holding the select signal and dispatching the temporarily recorded and held data through the data bus 9 to the CPU 1 and each time the CPU 1 reads the temporarily recorded and held data from the monitoring register 6, after reading, the monitoring register 6 clears the temporarily recorded and held data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of monitoring a selection decoder for incorporating a central processing unit, and selecting a peripheral device of the central processing unit when the central processing unit accesses the peripheral device, and an information processing apparatus thereof.

[0002]

2. Description of the Related Art A central processing unit (hereinafter referred to as CPU
A peripheral device such as a memory ROM, a memory RAM, or an input / output register (hereinafter, the input / output register is abbreviated as I / O.Reg) is mainly decoded by a decoder (Decoders / Demulti
plexers) and programmable logic devices (Programmable Logic Devic
e) (hereinafter programmable logic device is abbreviated as PLD) is used. Of these, it is possible to create a test pattern for programming the PLD and check the validity of the decoding circuit.However, fault monitoring during normal operation of the PLD on the actual device or during operation is currently performed especially. Absent.

[0003]

In an information processing apparatus in which a CPU is currently incorporated, a read / write check (read written data is performed by a firmware process of a memory ROM, a memory RAM, and an I / O.Reg. By checking that they match, the main CPU peripheral devices (ROM, RAM, I / O.Reg) are monitored.

However, when the device decoding the peripheral device is abnormal, the CPU cannot normally access the peripheral device. The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and to monitor a device decoding a peripheral device to limit a defective portion of hardware more narrowly. It is to provide a method that can be detected.

[0005]

To achieve the above object, in the first invention, a central processing unit having an address bus and a data bus, a peripheral device of the central processing unit connected to the bus, A decoder that decodes the address data of the address bus and outputs a selection signal that selects a peripheral device of the central processing unit, and a central processing unit that temporarily records and holds the selection signal and temporarily records and holds the data via the data bus. Consists of a monitoring register to be passed to
Each time the central processing unit reads the temporarily recorded and held data from the monitoring register, the monitoring register shall clear the temporarily recorded and held data after the reading.

In the second invention, a central processing unit having an address bus and a data bus, a peripheral device of the central processing unit connected to the bus, and address data of the address bus are decoded to decode the central processing unit. A decoder that outputs a selection signal that selects a peripheral device, a monitoring register that temporarily records and holds the selection signal and passes the data that is temporarily recorded and held via a data bus to the central processing unit, and the central processing unit monitors Each time the data temporarily recorded and held is read from the register, the monitoring register is provided with a clearing means for clearing the temporarily recorded and held data after the reading.

[0007]

According to the present invention, in the present invention, when the central processing unit outputs the address data and accesses the peripheral device of the central processing unit, the decoder decodes the address data and selects the peripheral device. Is output. The monitoring register temporarily records and holds the selection signal output from the decoder, and the central processing unit reads the data temporarily recorded and held in the monitoring register via the data bus. The central processing unit temporarily accesses the access data and the monitoring register that the central processing unit has accessed the peripheral device during the period from the time of reading the contents of the previous monitoring register to the reading of the contents of the monitoring register this time. The decoder can be monitored by comparing the recorded and held data.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram of an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a flow chart of a processing program of the information processing apparatus, and FIG. 3 is a flow chart of decoder monitoring processing. In FIG. 1, reference numeral 1 denotes a CPU, and memory ROM2, RAM3 and input / output registers (I / O.Reg) 4 which are CPU peripheral devices via an address bus 8 and a data bus 9.
, And the decoder (PLD) 5 and the monitoring register 6 are connected. Decoded output of decoder 5 10-12
Is the memory that is the CPU peripheral device to be selected.
It is connected to the chip select terminal bar CS of the ROM2, RAM3 and input / output register (I / O.Reg) 4. Also, the decoded outputs 10-12 are for monitoring the decoder output,
It is connected to the input circuit of the monitoring register 6 and, in the illustrated example, is connected to the input circuit of a latch circuit 6a composed of a flip-flop (FF) or the like.

In the above configuration, the CPU 1 outputs the address data of the CPU peripheral device to be selected on the address bus 8, and this data is decoded by the decoder 5,
The pulse output (any one of 10 to 12) is output. For example, when the CPU 1 wants to select the memory ROM 2, the pulse output 12 of the decoder 5 changes from high level to low level.
It switches to the level and the memory ROM2 is selected. Further, when it is desired to select the memory RAM 3 or I / O.Reg) 4, the pulse output 11 or the output 10 of the decoder 5 is switched from the high level to the low level, and the corresponding peripheral device is selected. Pulse output of this decoder 5 (10 to 12)
Is a flip-flop which is an input circuit of the monitoring register 6.
When the corresponding pulse output becomes low level in 6a, it is latched. The CPU 1 can read the selection information of the peripheral device by reading the data of the monitoring register 6 via the data bus 9. The CPU 1 can constantly monitor the presence or absence of an abnormality in the decoder 5 by comparing the selection information data of the peripheral device with the data accessed to the peripheral devices (2 to 4) so far.

Further, the monitoring register 6 resets the data of the flip-flop (FF) of the latch circuit 6a from the control line 13 after the data temporarily stored and held is read by the CPU 1, so that the CPU 1 can operate next time. The data of can be monitored accurately. 2 is a flowchart of a processing program of the information processing apparatus, and FIG. 3 is a flowchart of decoder monitoring processing.

In FIG. 2, the abnormality monitoring processing of the decoder is processed in the initial processing program 20 and the normal operation processing program 50. First, the initial processing program 20 will be described. When the information processing apparatus is started up by turning on the information processing apparatus, for example, the initial processing program 20 flows to the information processing apparatus, and the CP is processed in step S21.
U Initial setting is performed, and in step S22, the decoder monitoring process described below is performed. If there is an abnormality NG, an error handling program
At 30, error processing is performed and, for example, the cause of the error is displayed. The decoder monitoring process in step S22 is OK.
If so, the peripheral device monitoring process of step S23, for example, the read / write check of the memory or the like is performed based on the built-in test program. If there is an abnormal NG in the peripheral device monitoring process, error processing is performed by the air processing program 30 described above, and if normal, the process proceeds to step S24, peripheral device settings and memory clear are performed, and The operation shifts to the normal operation processing program 50 which is the mechanism operation of.

The normal operation processing program 50 is operated as pre-programmed processing programs 51, 52, ..., And predetermined information processing is performed. When the constant monitoring processing program 60 which is the decoder abnormality monitoring processing program is inserted into this processing program, when the processing program comes to this program, the same abnormality monitoring processing of step S61 described in steps S22 and S23 is performed. Decoder monitoring processing and peripheral device monitoring processing in step S62 are performed
If there is NG, the error processing is performed by the error processing program 30, and if there is no abnormality, the processing program (51, 52, ...) Is continuously processed.

FIG. 3 shows the above-mentioned decoder monitoring processing step S2.
2 shows the flowchart of S61. In FIG. 3, the area of the memory ROM 2 is accessed by the address data from the CPU 1 in step S71, the data of the monitoring register 6 is read into the CPU 1 in step S72, and the step S7
At 3, CPU1 can know whether ROM2 was correctly selected. ROM selection? When is NO, the NG is passed to the error processing program 30 as a decoder failure in step S70.
ROM selection in step S73? If Yes, then memory
The process shifts to the check of RAM3, the area of RAM3 is accessed in step S74, the data of the monitoring register 6 is read into the CPU1 in step S75, and the CPU1 can know whether the RAM3 was correctly selected in step S76. RAM selection? When is NO, the NG is passed to the error processing program 30 as a decoder failure in step S70. RAM selection in step S76? If is Yes, then the I / O.Reg4 input / output register is checked, the I / O.Reg4 area is accessed in step S77, and the monitoring register 6 data is accessed in step S78.
Read to CPU1, CPU1 I / O.Reg4 in step S79
It is possible to know whether or not was selected correctly. I / OR
eg4? Is NO, it means that the decoder in step S70 is defective.
Pass NG to the error handling program 30. I / in step S79
O.Reg 4 choice? If Yes, the continuation process is performed to the corresponding program shown in FIG. 2, for example, the peripheral device monitoring program in step S23 or the peripheral device monitoring program in step S62.

[0014]

According to the present invention, by constantly monitoring the decoder that selects the CPU peripheral device, the reliability of the information processing apparatus is improved and the hardware failure analysis is further facilitated. Since hardware failure analysis becomes easier, debugging efficiency can also be improved by incorporating this monitoring function in the test program during hardware debugging.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram illustrating a concept of an information processing device according to an embodiment of the present invention.

FIG. 2 is a flowchart of a processing program of the information processing device.

FIG. 3 is a flowchart of a decoder monitoring process.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 I / O.Reg 5 Decoder 6 Monitoring register 6a Latch circuit 8 Address bus 9 Data bus 10 to 12 Output signal 13 Control line

Claims (2)

[Claims] 1. A central processing unit comprising an address bus and a data bus, a peripheral device of the central processing unit connected to the bus, address data of the address bus is decoded, and the peripheral of the central processing unit is decoded. A decoder for outputting a selection signal for selecting a device; and a monitoring register for temporarily recording and holding the selection signal and passing the data temporarily recorded and held via the data bus to the central processing unit. Each time the central processing unit reads the temporarily recorded and held data from the monitoring register, after the reading, the monitoring register clears the temporarily recorded and held data. A method of monitoring a selection decoder for selecting a peripheral device of a processing device. 2. A central processing unit having an address bus and a data bus; a peripheral device of the central processing unit connected to the bus; and address data of the address bus for decoding to provide the peripheral of the central processing unit. A decoder which outputs a selection signal for selecting a device; a monitoring register which temporarily records and holds the selection signal and transfers the temporarily recorded and held data to the central processing unit via the data bus; Each time the processing device reads the temporarily recorded and held data from the monitoring register, after the reading, the monitoring register includes a clear unit that clears the temporarily recorded and held data. Information processing device.