JPS6220960Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an internal memory such as ROM or RAM.

Conventionally, in semiconductor integrated circuit devices that execute a program written in internal memory, even if the contents of the memory are used only internally, it is called a test circuit to check the contents from the outside. A memory address was given, and the contents of that address were output to the outside to check the contents. However, giving an address from the outside and checking the contents has the disadvantage that it is not possible to shorten the test time to check the contents (the time required to give the address from the outside and process it internally), and after checking the contents of the memory. Once the device is shipped, a third party can freely access the contents of the program written in the memory using the readout circuit, and especially in general-purpose microcomputers, instructions and instruction codes are Because it is published,
This had the serious drawback that not only the program data itself, but also the secrets of the program's know-how, etc., were leaked.

Therefore, without this test function, program confidentiality is completely maintained, but removing this function from the device makes it impossible to confirm whether the program written in memory is correct, and the device This results in lower reliability and higher defective rate. Furthermore, when the device itself is a semiconductor integrated circuit, this causes a major inconvenience in that defects in the elements cannot be detected.

The purpose of this invention is to create a semiconductor integrated circuit device that can maintain the confidentiality of program contents and know-how from third parties without impairing the test function of outputting the program contents written in memory to the outside. Our goal is to provide the following.

A semiconductor integrated circuit device according to the present invention includes a memory that stores data, a memory output control circuit that outputs specified stored data from the memory in response to a first signal, and an external device that continuously outputs the stored data to the outside. a readout circuit; a start address storage circuit that stores the start address information in the memory of the stored data that is continuously output; A switching circuit for instructing continuous output.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention in which a ROM is used in the memory section will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention, in which a central processing unit (CPU) performs data arithmetic processing and control.
1, data memory (RAM) 2, input/output device (I/O) 3 that transfers data with peripheral devices (keyboard, printer, etc.), external readout circuit (RTO) 4 included in the present invention, and program memory ( ROM) 5 are connected to each other by an internal bus 14. This invention further uses a jump address register (JMP) to store the jump address of branch instructions, etc.
6. A start address register (STA) 7 indicating the start of the memory address to be output to the outside, and a switching circuit (EXC) 8 for switching and selecting the two addresses during testing, and receiving the output from the switching circuit 8. A program counter (PC) 9 that stores and increments, and an address decoder (AD) 10 that receives the output of the program counter 9 and decodes it as an address of the ROM 5.
The memory output control circuit (MOC) 50 is configured to control the ROM 5. Here, a signal 11 is a load signal (LD) received from the central processing unit 1 to load the output from the switching circuit 8 into the program counter 9, and a signal 12 is received from the central processing unit 1 to increment and update the program counter. The increment signal (INC) and the signal 13 are test signals (TEST) used to check the contents of the ROM 5, and are used to switch between the two types of output (JMP and STA). Further signal 15
is an address signal generated by an instruction decoded by the central processing unit 1.

FIG. 2 shows a specific example of the switching circuit 8 and its peripheral circuits, with test-related circuits extracted. Elements that are the same as in FIG. 1 are given the same reference numerals. This will be explained below with reference to the drawings. now
A program according to a user's request is stored in the ROM 5, and in a normal use mode, the test signal 13 is "0" and the jump address register 6 for storing the jump address of a branch instruction, etc. is selected.
When the branch instruction issued from the ROM 5 is fetched and decoded by the central processing unit 1, the load signal 11 from the central processing unit 1 becomes active, the jump address is loaded into the program counter 9, and the branch instruction is read through the address decoder 10. ,ROM
5 is selected, its contents are output to the internal bus 14, and further taken into the central processing unit 1,
be deciphered. Also, in cases other than branch instructions, the increment signal 12 is used instead of the load signal 11.
becomes active, the contents of the program counter 9 are updated, the contents of the ROM 5 are output to the internal bus 14, and the above operations are repeated.

Now, when the TEST signal 13 becomes "1" and enters the test state, the switching circuit 8 selects the start address register 7 that stores the output start address, and when the load signal 11 becomes active, the switch circuit 8 selects the start address register 7 that stores the output start address. The contents are loaded into the program counter 9 and sent to the ROM 5 via the address decoder 10, and the contents of the ROM 5 are sent to the external read circuit 4 via the internal bus 14. Then, by sequentially activating the increment signal 12, the contents of the program counter 9 are updated, and the contents of the ROM 5 are accordingly sent to the external reading circuit 4, and confirmed by reading the contents from the outside. (See Figure 3). That is,
ROM indicated by the start address register 7
By sequentially outputting to the outside from address 5
The contents of ROM5 are confirmed. However, if the address of the ROM 5 of the output content is unknown, the content will not be confirmed, and only the program designer can compare it with the expected value and check whether it is correct. In other words, even if a third party can know the output content itself, it is unclear whether it is data or instructions, and furthermore, it is unclear at what address the output is stored. Since the address is unknown, the program flow cannot be known.

Furthermore, by configuring the start address register 7 in the same way as the ROM 5, which is configured according to the user's request, it becomes impossible to rewrite it from the outside or read it directly, and the user decides the start address to be read for each code. The address is completely unknown to third parties, so confidentiality can be maintained, and testing time can be shortened by continuously outputting the contents.

In the above embodiment, the jump address register 6, the start address register 7, and the switching circuit 8 are included in the memory output control circuit 50, but even if these exist in the central processing unit 1, the registers are The same function can be achieved even if they are part of the instruction register or if they are independent devices.

As detailed above, the present invention makes it possible to maintain confidentiality by providing a reading circuit from memory and a circuit for storing the first address of the output, and making that address unknown to a third party. Effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit element constructed according to the present invention, FIG. 2 is an explanatory diagram showing a specific circuit extracted from FIG. 1 and its peripheral parts for explanation of operation, FIG. 3 is an explanatory diagram showing the test procedure. 1... Central processing unit (CPU), 2... Data memory (RAM), 3... Input/output device (I/O), 4
...External read circuit (RTO), 5...Program memory (ROM), 6...Jump address register (JMP), 7...Start address register (STA), 8...
...Switching circuit (EXC), 9...Program counter (PC), 10...Address decoder (AD), 11
...Load signal (LD), 12...Increment signal (INC), 13...Test signal (TEST), 1
4...Internal bus, 15...Address signal, 50...Memory output control circuit (MOC).

Claims (1)

[Scope of utility model registration request] a memory for storing data; a memory output control circuit for outputting specified stored data from the memory in response to a first signal; an external reading circuit for continuously outputting the stored data to the outside; a first address storage circuit that stores the first address information of the stored data in the memory; and a switching circuit that switches from address information in a normal use mode to the first address information and instructs the continuous output by a second signal. A semiconductor integrated circuit element comprising: