JPS5933200U - semiconductor integrated circuit element - Google Patents
semiconductor integrated circuit elementInfo
- Publication number
- JPS5933200U JPS5933200U JP1982125587U JP12558782U JPS5933200U JP S5933200 U JPS5933200 U JP S5933200U JP 1982125587 U JP1982125587 U JP 1982125587U JP 12558782 U JP12558782 U JP 12558782U JP S5933200 U JPS5933200 U JP S5933200U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- semiconductor integrated
- integrated circuit
- circuit
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案により構成される半導体集積回路素子の
一実施例を示すブロック図、第２図は動作説明のために
第１図より抜き出した具体回路とその周辺部とを示す説
明図、第３図はテストの手゛順を示す説明図である。
１・・・・・・中央処理装置（ＣＰＵ）、２・・・・・
・データメモＩＪ （ＲＡＭ）、３・・・入出力装置（
Ｉｌｏ）、４・・・・・・外部読出回路（ＲＴＯ）、５
・・・・・・プログラムメモリ（ＲＯＭ）、６・・・・
・・飛び先番地レジスタ（ＪＭＰ）、７・・・・・・先
頭番地レジスタ（ＳＴＡ）、８・・・・・・切換回路（
ＥＸＣ）、９・・・・・・プログラムカウンタ（ＰＣ）
、１０・・・・・・アドレスデコーダ（ＡＤ）、１１・
・・・・・ロード信号（ＬＤ）、１２・・・・・・イン
クリメント信号（ＩＮＣ）、１３・・・・・・テスト信
号（ＴＥＳＴ入 １４・・・・・・内部バス、１５・・
・・・・番地信号、５０・・・・・・メモリ出力制御回
路（ＭＯＣ）。FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit element constructed according to the present invention, FIG. 2 is an explanatory diagram showing a specific circuit extracted from FIG. 1 and its peripheral portion for explaining the operation, FIG. 3 is an explanatory diagram showing the test procedure. 1...Central processing unit (CPU), 2...
・Data memo IJ (RAM), 3...I/O device (
Ilo), 4...External readout circuit (RTO), 5
...Program memory (ROM), 6...
...Jump address register (JMP), 7...Start address register (STA), 8...Switching circuit (
EXC), 9...Program counter (PC)
, 10...address decoder (AD), 11.
... Load signal (LD), 12 ... Increment signal (INC), 13 ... Test signal (TEST input), 14 ... Internal bus, 15 ...
...Address signal, 50...Memory output control circuit (MOC).
Claims (1)
リから指定された格納済データを出力させるメモリ出力
制御回路と、前記格納済データを外部へ連続出力する外
部読出回路と、前記連続出力される前記格納済データの
前記メモリにおける先頭番地情報を格納する先頭番地格
納回路と、第２の信号により通常の使用モードの番地情
報から前記先頭番地情報へ切換えると共に前記連続出力
を指示する切換回路とを含むことを特徴とする半導体集
積回路素子。a memory for storing data; a memory output control circuit for outputting specified stored data from the memory in response to a first signal; an external reading circuit for continuously outputting the stored data to the outside; a first address storage circuit that stores the first address information of the stored data in the memory; and a switching circuit that switches from address information in a normal use mode to the first address information and instructs the continuous output by a second signal. A semiconductor integrated circuit element comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982125587U JPS5933200U (en) | 1982-08-19 | 1982-08-19 | semiconductor integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982125587U JPS5933200U (en) | 1982-08-19 | 1982-08-19 | semiconductor integrated circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933200U true JPS5933200U (en) | 1984-03-01 |
| JPS6220960Y2 JPS6220960Y2 (en) | 1987-05-27 |
Family
ID=30285864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982125587U Granted JPS5933200U (en) | 1982-08-19 | 1982-08-19 | semiconductor integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933200U (en) |
-
1982
- 1982-08-19 JP JP1982125587U patent/JPS5933200U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6220960Y2 (en) | 1987-05-27 |
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