JPS5839650U - Judgment device - Google Patents
Judgment deviceInfo
- Publication number
- JPS5839650U JPS5839650U JP13435581U JP13435581U JPS5839650U JP S5839650 U JPS5839650 U JP S5839650U JP 13435581 U JP13435581 U JP 13435581U JP 13435581 U JP13435581 U JP 13435581U JP S5839650 U JPS5839650 U JP S5839650U
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- register
- circuit
- instruction
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の判定装置の実施例の回路図である。
１・・・第１の記憶装置、３・・・デコーダ、５，６・
・・切り換え回路、９・・・第２の記憶装置。The figure is a circuit diagram of an embodiment of the determination device of the present invention. DESCRIPTION OF SYMBOLS 1... First storage device, 3... Decoder, 5, 6.
...Switching circuit, 9...Second storage device.
Claims (1)
から読み出した命令を格納するレジスタ１と、レジスタ
１に格納された命令コードをデコーダを通して該命令の
長さを識別する回路と、該デコーダの出力をデータとし
、第１の記憶装置のアドレスの一部で切り換える切り換
え回路と、第２の記憶装置からの読出しデータを格納す
るレジスタ２と、レジスタ２と該切り換え回路とのＯＲ
回路を具備し、該ＯＲ回路を第２記憶装置の入力データ
とし、第１の記憶装置のアドレスの一部を第２の記憶装
置のアドレスとすることにより、第１の記憶装置に格納
されている命令の通過部分の判定を行なうことができる
ように構成されてなることを特徴とする判定装置。A first storage device, a second storage device, a register 1 that stores an instruction read from the first storage device, and a circuit that identifies the length of the instruction by passing the instruction code stored in the register 1 through a decoder. , a switching circuit that uses the output of the decoder as data and switches based on a part of the address of the first storage device, a register 2 that stores read data from the second storage device, and a combination of the register 2 and the switching circuit. OR
A circuit is provided, the OR circuit is used as input data of the second storage device, and a part of the address of the first storage device is used as the address of the second storage device, so that the data stored in the first storage device is A determining device characterized in that it is configured to be able to determine a passing portion of an instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13435581U JPS5839650U (en) | 1981-09-11 | 1981-09-11 | Judgment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13435581U JPS5839650U (en) | 1981-09-11 | 1981-09-11 | Judgment device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5839650U true JPS5839650U (en) | 1983-03-15 |
Family
ID=29927783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13435581U Pending JPS5839650U (en) | 1981-09-11 | 1981-09-11 | Judgment device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839650U (en) |
-
1981
- 1981-09-11 JP JP13435581U patent/JPS5839650U/en active Pending
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