JPH0333940A - Microprocessor for evaluation - Google Patents

Abstract

PURPOSE:To easily conform a data write bus cycle to an instruction that becomes the cause of it by outputting a control signal for write cycle correction which goes to an ineffective level when a store data write bus cycle is generated. CONSTITUTION:When the correspondence of the data write bus cycle using the control signal(BUSY) 8 for write cycle correction to the instruction that becomes the cause is performed, the signal 8 is outputted to a trace device, and is stored with bus cycles generated at an address bus 9 and a data bus 10. Next, after the operation of the trace device is completed, the data write bus cycle is searched from stored trace data. At this time, the signal 8 being traced simultaneously represents an effective level, and the bus cycle(instruction fetch bus cycle) in which the signal 8 goes to the ineffective level first in the bus cycle generated before the data write bus cycle is searched. Then, the correspondence of the data write bus cycle to the instruction that becomes the cause is attained by referring to queue depth stored simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an evaluation microprocessor, and more particularly to means for correcting execution trace data of an evaluation microprocessor having a pipeline architecture.

[Conventional technology]

In general, an evaluation microprocessor operates exactly the same as the microprocessor to be evaluated, and is furthermore equipped with a debugging function for outputting various control signals and operation status inside the device to the outside of the device. Therefore, by operating such an evaluation microprocessor on a target system and monitoring its debug function, it is possible to grasp the internal operation of the device and easily analyze the execution process of the device. It becomes possible.

This type of evaluation microprocessor is not actually directly integrated into a target system and used, but is usually used in a microprocessor development support device called an in-circuit emulator. This in-circuit emulator basically stores this evaluation microprocessor and an evaluation program (a program that runs on the target system), and has a program memory that enables it to be executed by the evaluation microprocessor. The microprocessor includes a microprocessor, a break circuit that stops execution of the microprocessor according to a predetermined specific condition of the processor, and a trace device that stores the execution process of the processor.

That is, the evaluation microprocessor executes the evaluation program within an in-circuit emulator, and direct interface with the target system is performed via a cable called a probe. This probe is connected to the target system where the microprocessor to be evaluated is originally installed.

By executing the evaluation program using such an in-circuit emulator and at the same time tracing the actual bus operation (bus cycle) of the evaluation microprocessor and the aforementioned depacking function (information), the evaluation program The execution process can be verified.

There are two methods for verifying the evaluation pro gamer 11 using this tracing device.

The first method starts execution of the evaluation microprocessor from a specified point and stops execution at a specified specific point 1.about. That is, it is put into a standby state using an interrupt or the like. At this time, the trace device stores the bus cycle and depack information from the start to the stop of the processor, and by referring to these, the program is verified.

The second method basically traces only the sections or points that match specified specific conditions without stopping the execution of the evaluation processor.

The first method is convenient for verifying the macro flow of a program. However, the storage capacity of a trace device is generally limited to 2 to 4 steps, so when verifying a long program, it is necessary to divide the program into several parts. Therefore, it is useful for initial logic verification of a program, but is unsuitable for verification of a real-time program that uses many interrupts (stopping the processor is undesirable).

On the other hand, in the second method, by tracing only a specific section or point, it is possible to verify the program without greatly limiting the storage capacity of the tracing device.
Also, trace contents can be verified without stopping the processor. That is, it is only necessary to refer to the memory contents of the trace device while the processor is running in the background, and is therefore useful for verifying programs in real-time systems. However, since it is a trace of only a specific section or point, it is not suitable for verifying the entire evaluation program.

As described above, since both the first method and the second method have advantages and disadvantages, in-circuit emulators usually have the functions of both.

Next, the data stored in the trace device is the bus cycle and depacking information of the evaluation microprocessor, as mentioned above, and basically these trace result data can be displayed as they are using a display device, etc. , disassemble it, and display it in monic format.

The bus cycle data displayed in this manner indicates the actual bus operation of the evaluation microprocessor.

This method of displaying trace result data is used for program verification of relatively low-level microprocessors that do not have an instruction fetch queue or the like and do not perform pipeline operations. In other words, by storing the M1 signal (debug information) that is normally output in synchronization with the first execution of an instruction code together with the fetch data when fetching the code, disassembly processing is performed on the trace result data using this M1 signal as a guide. In a microprocessor that does not perform pipeline operation and has an instruction fetch queue, the bus operation itself is synchronized with the execution unit operation.

On the other hand, in high-level microprocessors that have an instruction fetch queue and adopt a pipeline architecture, program verification is possible by displaying the actual bus operation of the evaluation microprocessor as described above, or even by disassembling it. It can't be achieved.

This is because the following problems occur.

(1) When a branch instruction 1 interrupt or the like is executed and the program flow changes, the instruction code prefetched into the instruction queue is not executed and is discarded. However, as long as only the actual bus operations of the evaluation microprocessor are traced and displayed, even the discarded instructions will appear to have been executed.

(2) As mentioned above, the trace result data is disassembled and displayed using the M1 signal as a guide, but the fetch bus cycle of the instruction code in which the M1 signal is output from the storage device to the instruction queue is at the beginning of the instruction code. This does not indicate that this is the case. This is because the Ml signal at this time is
This is a signal that is output in synchronization with the first execution of an instruction code that has already been prefetched into the instruction queue, and this M1
There is no relationship between signals and instruction code fetch bus cycles. Therefore, it is not possible to simply disassemble using the M1 signal as a guide.

(3) An execution unit that processes instructions (instruction decoding and associated arithmetic processing, register transfer, etc.);
In high-level microprocessors where the bus control unit (BCU), which performs data access processing for storage devices, performs completely pipeline operation, the CP
As long as only the actual bus operation of the evaluation microprocessor is traced and displayed, the relationship between the data access operation processed by the U unit and passed to the BCU and the instruction that caused the access operation cannot be understood. .

For example, when the CPU writes data in register A to the storage device as a result of processing an instruction, the CPU writes data in register A to the storage device.
A data store request is sent to J, and the receiver passes the store data to the BCU (writes the data in register A to the write buffer in the BCU), and at the same time starts processing the next instruction.Meanwhile, the BCU transfers the store data. Write to the storage device at an appropriate timing.When loading data from the storage device, the CPU section does not start processing the next instruction unless the load data is delivered to the CPU section, so the BC
The operations of U and CPU maintain a synchronous relationship.

For microprocessors with such a pipeline architecture, in order to verify the program execution flow rather than the device operation level, it is necessary to verify the actual bus operation and depack information of the evaluation microprocessor stored in the trace device. , it is necessary to arrange and display only programs executed using software in an easy-to-understand format.

Specifically, the following software operations are required.

1) Fetch data that has been prefetched into the instruction queue and has not been executed is deleted and not displayed. 2> The trace result data of the bus cycle is associated with the fetch cycle (Ml cycle) indicating the beginning of the instruction code. Also, disassembly is performed based on the associated M1 cycle and a binary display is performed.

3) Correlate the data read/write access frame to the storage device with the instruction (2) that caused the access frame (dimonic display).

In order to realize the above-mentioned software operations, the following technique called cue tracking is generally used.

In queue tracking, the number of unexecuted instructions that have been prefetched into a queue (queue depth - queue depth) is always stored in the trace device, and this queue depth is used to perform software I/ware operations. It is a method.

Regarding queue depth generation, a signal (queue light signal) indicating that N instructions have been written to the queue, which is depack information from the evaluation microprocessor, is normally used.
A signal indicating that an instruction has been read from the queue (queue read signal) and a signal indicating discarding all instructions stored in the queue (queue flush signal) are output. Use the counter (created with an external circuit) to count up and down.
This is achieved by clearing.

Next, regarding the software operations in the three steps 1) to 3) described above, a specific method using queue 1 to racking in the prior art will be described below.

■Branch instruction 1 When the program flow changes due to execution of an interrupt, etc., when fetching the first instruction code of the branch destination,
The queue depth immediately before the queue is flushed is output to the trace device, and the queue depth value is stored at the same time as this fetch bus cycle (branch bus cycle).Therefore, for trace result data, the branch bus cycle is By searching and referring to the queue depth at that time, the number of instructions that were discarded from the queue without being executed can be obtained, and that fetch bus cycle is deleted from the trace result data.

(2) Output and store the cue depth when the M1 signal is output to the trace device. Therefore, by searching for the M1 signal in the trace result data and referring to the queue depth at that time, the first opcode of the instruction code to be prefetched into the instruction queue and executed and the opcode stored in the trace device can be determined. Associate fetch bus cycles. The fetch bus cycle that occurred the queue depth before the M1 signal was output is the first fetch bus cycle of the instruction.
This becomes a code fetch cycle.

(2) Regarding data read/write access frames for the storage device, use separate methods to associate data read accesses and data write accesses with the instructions that caused them.

For data read access, the queue depth at the time the data read bus cycle occurs is stored in the trace device. Therefore, by searching the trace result data for a data read bus cycle and referring to the queue depth at that time, the instruction that caused the data read bus cycle is associated. The fetch bus cycle that occurred a queue depth indicated by the data read bus cycle indicates the instruction code set that caused the fetch bus cycle.

In a data write access, as described above, there is no correlation between the CPU operation and the BCU operation, so the queue depth at the time of this data write access has no meaning. Therefore,
The correspondence between the data write bus cycle of trace result data and the instruction that caused this is performed as follows.

(a) Outputs the store data write cycle from the CPU section to the write buffer in the BCU (outputted from the evaluation microprocessor as depack information) to the trace device, stores it, and also stores the queue depth value at that time. Remember it as well.

(b) Search for the write cycle in (a) for the trace result data, and at the same time search for the first data write bus cycle that occurs after that to make a correspondence.

(c) By referring to the queue depth at the time of the write cycle in (a) above, the instruction that caused the write cycle is associated. Indicates the instruction code set caused by the fetch bus cycle that occurred the queue depth indicated by the write cycle.

(d) Using both the correspondence between the write cycle and the instruction that caused it in (c) and the correspondence between the data write bus cycle and the write cycle in (b), identify the data write bus cycle and its cause. Match the commands that have been created.

As shown above, arranging trace result data using software is essential for program verification of high-level microprocessors that have an instruction fetch queue and employ a pipeline architecture.

[Problem that the invention seeks to solve]

In this way, a high-level microprocessor that has an instruction fetch queue and uses a pipeline architecture,
When verifying the flow of program execution, conventional software operations related to the correspondence between data write I/bus cycles for storage devices and the instructions that caused them include store data write cycles from the CPU section to the write buffer in the BCU. and the cue depth at that time must be stored in the trace device. However,
The trace information regarding this write cycle is data necessary for correcting the bus cycle of a processor that performs a pipeline operation, and is not directly needed by a program evaluator. Therefore, there is a drawback that the trace capacity (depth) available to the program evaluator is apparently reduced.

For every data write bus cycle, there is always a write cycle that is unnecessary for a pair of program evaluators, so this unnecessary trace information cannot be ignored in a program that frequently uses data transfer and the like.

Furthermore, since this write cycle itself must be stored in the trace device, the trace capacity (width) must be increased. Generally, information indicating this write cycle is outputted to the outside of the device using five to six status terminals as depacking information of the evaluation microprocessor. Therefore, there is a disadvantage that these terminals must be traced extra.

On the other hand, in a microprocessor that has two stages of write buffers in the form of a queue in the BCU, when tracing is performed only in the section that matches the specified conditions for the evaluation microprocessor described in the conventional technology, the conventional data In software arrangement related to the correspondence between write bus cycles and the instructions that caused them, there are problems in which the correspondence is extremely difficult.

For example, in an evaluation microprocessor,
When a bus cycle as shown in a) occurs, and at the same time the trace device stores the bus cycle only in the section shown in FIG. 6(b), with this trace information alone, the data write bus cycle j 16m 34 on BCU write buffer write cycle. The decision is made in a way that corresponds to the

However, in reality, as shown in FIG. 6(a), the data write bus cycle tt6 corresponds to the BCU write buffer write cycle itself 2, and therefore, in the conventional software operation method, section tracing is not performed. In this case, there is a drawback that it is basically impossible to correct the write bus cycle.

An object of the present invention is to eliminate such drawbacks and to enable data write bus cycles to the storage device and instructions that caused them to be linked without using depack information regarding store data write cycles from the CPU section to the write buffer in the BCU. Therefore, there is no need to trace depack information related to write cycles using a trace device, and even if a specific interval trace is performed on a microprocessor with two stages of write buffers in the BCU, data write bus cycles and their It is an object of the present invention to provide an evaluation microprocessor in which it is possible to easily associate instructions that cause problems.

[Means for Solving the Problems] The configuration of the present invention includes an execution unit consisting of a CPU, an instruction fetch queue, and a write unit that temporarily holds stored data according to a data store request from the instruction fetch queue and the execution unit to a storage device. A bus control unit having a buffer and connected to an address bus and a data bus is provided, and the write operation of store data in the write buffer is performed in an arbitrary bus cycle, thereby verifying a high-level microprocessor using a big-line architecture. In the evaluation microprocessor, when a data store operation occurs from the execution unit to the write buffer, the state becomes a valid level and this state is maintained, and when the store data write bus cycle from the write buffer to the storage device occurs, the state becomes an invalid level. The present invention is characterized by having a debugging circuit that outputs a control signal to the outside of the circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of internal hardware of an evaluation microprocessor according to an embodiment of the present invention. In this embodiment, a data write I and a
It is possible to generate a write cycle correction control signal necessary for software operations regarding the correspondence between a bus cycle and the instruction that caused the bus cycle, and to make the correspondence therebetween.

Execution Unit (CPU)], Bus Control Unit (BCu)2. Write buffer 3. The operation of instruction queue 4 is described in detail in the prior art.

Therefore, here, the write cycle correction control signal (BU
Only the operation of SY)8 and the software operation method using its signals will be described.

When a data store request is issued from the CPU to the storage device, valid data such as the store address and store data is output to the internal address data bus, and at the same time, the negative logic BCUCU internal write buffer 3 signal BWR5 becomes active and the write buffer 3 is Necessary data is written. On the other hand, the D-F was outputting a low level BUSY signal 8 due to the negative logic internal hardware reset signal 6.
F7 outputs a BUSY signal 8 at a valid level (high level) according to the trailing edge of the BWR signal 5.

Next, at an appropriate timing, a data write bus cycle occurs for the storage device of the store data in the write buffer 3, and along with valid data being output to the address bus 9 and data bus 10, the negative logic write signal WR12 becomes active. , at the trailing edge of its write signal 12, D-F
BUSY signal 8, which is the output of F7, outputs an ineffective level (low level).

Note that when the write buffer 3 is completely full, if a data store request is issued again from the CPU 1, the operation of the CPU is made to wait until the write buffer 3 becomes empty. A control signal that causes the CPU 1 to wait for a store operation is output from the BCU 2 via the internal control bus, and the BWR signal 5 does not become active.

FIG. 2 shows the relationship between the BUSY signal 8, which operates as described above, and the bus cycle of the evaluation microprocessor.

Next, an example of the bus cycle shown in FIG. 2 will be explained regarding the software operation method (trace data correction method) using the BUSY signal 8 to associate the data write bus cycle to the storage device with the instruction that caused it. I will explain using

The BUSY signal 8 shown in FIG. 2 is output to the trace device and stored together with bus cycles generated on the address bus 9 and data bus 10.

After the operation of the trace device is completed, a data write bus cycle (t in Figure 2) is selected from the stored trace data.
4).

At this time, the BUSY signal 8, which is raced from 1 to 8 at the same time, indicates a valid level.

Next, search for the bus cycle (corresponding to instruction fetch cycle 1 in FIG. 2) in which the BIJSY signal 8 is at an ineffective level for the first time among the bus cycles that occurred before this data write bus cycle 4. do.

This instruction fetch bus cycle is performed as in 11. 'f to 1
1. By referring to the stored queue depth, this data write bus cycle LL and the instruction that caused it are matched by 1.1. Command ff 1-bus 11 go/L1
indicates the instruction code set that caused the fetch bus cycle that occurred the queue depth indicated by .

This is because instruction fetch bus cycles 12, 1 . . . BUSY signal 8 indicates a valid level. is a bus cycle that occurred after the write cycle j1m to the BCU-write buffer was completed, and clearly the data write bus cycle 4 was not generated by these instructions.

Therefore, the correspondence can be made using the queue depth of the first bus cycle that occurs before (or simultaneously with) write cycle 70 to the BCU write buffer that is synchronized with CPU execution.

In this way, the BUSY signal 8 and queue depth (cue tracking circuit output) are connected to the address bus 9 and the data bus 1.
By outputting and storing the data write bus cycle to the trace device together with the bus cycle that occurs at 0, it is possible to easily associate the data write bus cycle for the storage device with the instruction that caused it.

FIG. 3 shows a block diagram of a trace section of a microprocessor development support device using such an evaluation microprocessor and software arrangement.

The evaluation microprocessor 20 of this embodiment has BUSY
This is an evaluation microprocessor that has a signal 8 output function.

A microprocessor development support device using this evaluation microprocessor 20 includes an address bus 9, a data bus 10. The depack information 11, the cue tracking circuit 22 output (cue depth), and the BUSY signal 8 are output to the trace device 23 and stored.

FIG. 4 shows a block diagram of the internal hardware of the evaluation microprocessor according to the second embodiment of the present invention. In this embodiment, a software operation is performed regarding the correspondence between a data write bus cycle and the instruction that caused it, for the storage device of a microprocessor that has write buffers 15 in a queue format in two stages (a) and (b) in the BCU 2a. The generation of control signals for write cycle correction necessary for this purpose and their correspondence are shown. CPU],,BCU2
, write buffer 15, and instruction queue 4 are the same as in the first embodiment.

Here, two burrow cycle correction control signals (BU
The operation of SY) 17.18 and the software operation method using these signals 17.18 will be explained.

As in the first embodiment, when the BWR5 signal becomes active and valid data such as a store address and store data is written into one of the write buffers 15, an internal hardware reset signal (negative logic) 6 causes BUSY signal 1 signal 16 SY signal 17 at ineffective level (low level)
The up-down counter 16, which had been outputting , is counted up by the trailing edge of the BWR signal 5, and outputs ``IJ, that is, the BUSY signal 17 is 1 (valid level) and the BUSY signal 1 signal 18 is ineffective level.

Next, when a data store operation occurs in one of the write buffers 15 again, the counter 16 counts up again, and the BUSY signal 17 becomes 1 (valid level) BU and the SY signal 181 (valid level). Output.

Note that if a data store request is issued again from the CPU in this state, the operation of the CPU is made to wait until the write buffer becomes empty, similar to that embodiment. (The BWR signal 5 does not become active.) On the other hand, when a write cycle of store data in the write buffer 15 occurs at an appropriate timing as in the first embodiment, the trailing edge of the write signal 12 causes Counter 6 is down-counted, and its output is 'IJ' (BUSY signal 17 is 1, B
tJSY signal 18 signal 18ro” (BUSY signal 17
becomes O, BUSY signal 1 signal 18. In other words, BtJS
The queue state of the write buffer 15 in a queue format with 17 Y signals, 1 BUSY signal, and 18 stages of signals is shown.

As described above, the relationship between the USY signals 17 and 18 and the bus cycle of the evaluation microprocessor is shown in the timing diagram of FIG.

Next, a software operation (trace\data correction method) regarding the correspondence between data write bus cycles using the BUSY signals 17 and 18 and the instruction that caused them will be explained using FIG.

Similarly to the first embodiment, the data write bus cycle (t16 in FIG. 5) is selected from the stored trace data.
and t18). BUSY signal 17. which is stored at the same time. Check the level of the BtJsY signal 18.

When data write bus cycle t16 occurs, BUSY signal 17. Both of the BUSY signals 18 indicate rll, indicating that the write buffer 15 is full. Therefore, the line 1 to bus cycle t16 is
This corresponds to the data store operation (BCU write buffer write cycle) two cycles ago. That is, in the bus cycle that occurred before this data write cycle tI6, the BUSY signal 17. By searching for the bus cycle just before the BUSY signal 18 indicates two count-up operations (corresponding to the tth cycle in Figure 5) and referring to the queue depth at that time, this data write bus cycle j+6 and its cause can be determined. Subtract the corresponding command by 1 inch. This correspondence is the same as in the first embodiment. Similarly, BUSY signal 17 when data write bus cycle t18 occurs
．． The BUSY signals 18 each indicate "1.+, ro", indicating that only one of the write buffers 15 is full of store data.

Therefore, the write bus cycle t's corresponds to the data store operation one cycle before. That is, in the bus cycle that occurred before this data write cycle t18, the BUSY signal 17. The immediately preceding bus cycle (corresponding to the tth cycle in FIG. 5) in which the BUSY signal 18 indicates one count-up operation is searched, and the queue depth at that time is referred to and similarly correlated.

As shown above, the BUSY signal 17. BUSY signal 18
and queue depth to the address bus 9. By outputting and storing the bus cycles generated on the data bus 10 to the trace device, data write bus cycles to the storage device of the evaluation microprocessor, which has two stages of write buffers in the form of a queue in the BCU, and their causes can be detected. Correspondence with other instructions can be easily realized.

In addition, as described in the conventional technology, only a certain section is
In the case of racing, even in cases that cannot be realized with conventional software arrangement (tracing the section shown in Figure 6 (b)), it is possible to correctly correspond to the write bus cycle and the instruction that caused it. Can be attached.

For example, in the case where only section X is traced in the bus cycle shown in FIG. 5, the instruction that caused data write bus cycle t16 is instruction fetch bus cycle j +2 t11+11.14. t15
Therefore, in the trace display when verifying the program execution process (the display after the software arrangement processing described in the prior art), data write bus cycle t16 may be deleted or displayed at the beginning. display can be excluded.

In the prior art software arrangement, data write cycle j+6 is associated with BCUCU write buffer write cycle t22, and is actually associated with the instruction that caused data write bus cycle t+8, for example, instruction fetch bus cycle 1□. I end up.

Incidentally, a configuration diagram of a trace section of a microprocessor development support apparatus using such an evaluation microprocessor and software arrangement can be considered to be similar to that shown in FIG.

〔Effect of the invention〕

As explained above, the evaluation microprocessor according to the present invention becomes a valid level when a data store operation occurs from the CPU section to the write buffer in BC1J, and becomes ineffective when a store data write bus cycle occurs from the write buffer to the storage device. Outputs the level control signal to the outside of the device. Therefore, by outputting the control signal to the trace device and storing it, the CPU section can transfer the data write bus cycle to the BCU, which was necessary in the software arrangement for associating the data write bus cycle to the storage device with the instruction that caused it. The storage capacity of the trace device (depth 1 width) is
This has the effect that it can be used effectively.

In addition, when tracing only a specified section in a microprocessor that has two stages of write buffers in the form of a queue in the BCU, it is difficult to match write bus cycles with the instructions that caused them, which was difficult to do with conventional technology. This has the effect that it can be easily realized (mislabeling can be eliminated).

[Brief explanation of drawings]

FIG. 1 is a block diagram of the internal hardware of a microprocessor for evaluation of an embodiment of the present invention, FIG. 2 is a timing diagram of write cycle control signals and bus cycles in this embodiment, and FIG. A block diagram of the trace section of a microprocessor development support device using the evaluation microprocessor of the embodiment, FIG. 4 is a block diagram of the second embodiment of the present invention, and FIG. 5 is the evaluation microprocessor of the present embodiment. Figure 6 (a)
) and (b) are schematic diagrams of examples of bus cycles and bus data stored in a trace device of a conventional evaluation microprocessor. 1... Execution unit (CPU), 2... Bus control unit (BCU), 3.15... Write buffer, 4... Instruction fetch queue, 5... B W
RfZ No. 6... Internal hardware reset signal, 7
...D-FF, 8, 17.18・ BUSY signal, 9
...Address bus, 10...Data bus, ]l...
・Depack information, 12...Write signal WR113・
...Read signal RD, 14...AND circuit, 16...
・Up/down counter, 20...Microbe IV Senosa for measurement 21...Program storage device for i-1 valence,
22, ·, A · -,, -tracking circuit, 23...
tracing device.

Claims (1)

[Claims] A bus control unit that is connected to an address bus and a data bus, and has an execution unit consisting of a CPU, an instruction fetch queue, and a write buffer that temporarily holds store data according to a data store request from the instruction fetch queue and execution unit to a storage device. In an evaluation microprocessor that performs a write operation of store data in the write buffer in an arbitrary bus cycle to verify a high-level microprocessor using a pipeline architecture, the data from the execution unit to the write buffer is The debugging circuit includes a debugging circuit that outputs to the outside of the circuit a control signal that becomes a valid level when a store operation occurs, maintains that state, and becomes an ineffective level when a bus cycle for writing store data from the write buffer to the storage device occurs. An evaluation microprocessor featuring: