JPS62221043A - Monitor circuit for logical unit - Google Patents

Abstract

PURPOSE:To obtain a monitor circuit for logical unit that can easily collect the sufficient data for study of the factor of abnormality, by connecting a monitor circuit containing a monitor processor, a local memory, a trace memory, a communication adaptor, etc. directly to the main bus of a device to be monitored. CONSTITUTION:The optimum monitor items are set by a microprogram in response to the hardware constitution of a logical unit 1. A WDT circuit 16 receives an access when a main processor 21 carries out a specific instruction in a working mode of the unit 1. If no access is supplied to the circuit 16 within a fixed time and no occurrence of abnormality is detected, the circuit 16 applies interruption to a monitor processor 11. While a trace memory control circuit 15 stops the tracing action to a trace memory 14 and outputs the data stored in the memory 14 to an external device 2 via a communication adaptor 13 and a communication line 19. The data output of the memory 14 is carried out via the circuit 19 and the unit 1 continues its working with no discontinuation of the normal operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a monitoring circuit for a logic device, and particularly to a monitoring circuit for a logic device used in an information processing device [Prior Art] Conventionally, the present invention relates to a monitoring circuit for a logic device used in an information processing device. A commonly used method for this is to execute a predetermined monitoring operation using a monitoring program created using a group of instructions or a group of microinstructions that control the logic device.

The monitoring program allows the monitored device to be accessed at regular intervals by software or firmware, and if the monitored device is not accessed within a preset period of time, reports the occurrence of an abnormality to the higher-level device, Display it on the own device or initiate a restart. However, the data collection necessary to determine the cause of the abnormal occurrence relies in part on logging functionality built into each 110 device control program.

[Problem that the invention seeks to solve]

In the conventional logical device monitoring method described above, data collection necessary to investigate the cause of abnormality is partially performed on each I10.
Since it relies on the logging function built into the device control program, it has the disadvantage that it cannot collect sufficient data and it may take a long time to resolve the problem.

Another disadvantage is that depending on the location where the abnormality occurs, log information stored in the memory of the monitored device cannot be retrieved.

Ideally, it would be possible to log detailed internal state transitions for each firmware that controls each monitored device, but due to the difficulty of modifying the details of already designed products, firmware capacity, and performance, it is difficult to log each monitored device itself. It is impossible to change.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a logic device monitoring circuit that can easily collect sufficient data to investigate the cause of an abnormality in a logic device.

[Means for solving problems]

A monitoring circuit for a logic device according to the present invention includes a communication means between a processor, a memory, and an external device, and a programming means for arbitrarily programming a monitoring function via this communication means.
a control means for controlling a bus trace operation of the monitored device and a maintenance diagnosis operation of the monitored device according to the monitoring function programmed by the programming means; and a control means for controlling a bus trace operation of the monitored device and a maintenance diagnosis operation of the monitored device; and output means for sending to an external device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of a logic device in which a monitoring circuit according to an embodiment of the present invention is installed. This logic device 1 includes a monitoring circuit 10, a main processor 21, and a main memory 22.
, I10 device group 23, and maintenance panel 24
and a main bus 25, and the monitoring circuit 10 is connected to an external device 2 (for example,
connected to a personal computer).

The monitoring circuit 10 is directly connected to the main bus 25 and is viewed by the main processor 21 as one I10 device. Further, the monitoring circuit 10 is housed in a package so that it can be added to an already designed device, and the logic device 1 is connected to the monitoring circuit 1.
If 0 is not implemented, the conventional operation is performed.

The main processor 21 controls the subordinate I10 device group 23 via the main bus 25 in accordance with commands from a host device or commands stored in the main memory 22 .

The maintenance panel 24 manually controls maintenance and diagnostic operations of the logical device 1.

The external device 2 is a device for storing the program of the monitoring circuit 10 and its monitoring results.

Referring to FIG. 1, the monitoring circuit 10 of the present embodiment shown in FIG.
1, a local memory 12 for storing the program of the monitoring processor 11, a communication adapter 13 for communicating with the external device 2, and a communication adapter 13 for storing the trace data of the main bus 25 of the logical device 1, which is the monitored device. A trace memory 14, a trace memory control circuit 15 that controls data input/output to the trace memo 1/4, a WDT (watchdog timer) circuit 16, and a main bus 25 of the logic device 1.
and a bus control circuit 17 that controls the communication between the monitoring circuit 10 and the local bus 18 of the monitoring circuit 10.

The monitoring circuit 10 is controlled by a microprogram stored in the local memory 12, but the microprogram stored in the local memory 12 can be arbitrarily set and changed by the external device 2 via the communication adapter 13 and communication line 19. It is possible.

The WDT circuit 16 is set to be accessed when the main processor 21 executes a specific instruction, and if it is not accessed within a certain period of time, it generates an interrupt to the monitoring processor 11 as an abnormality has occurred in the logic device 1 or the host device. .

The trace memory control circuit 15 controls the timing of trace on the main bus 25, and controls the trace timing on the main bus 25 at timings such as when fetching firmware instructions, accessing the main memory 22, and accessing the I10 device group 23.
Address signals, data signals, bus control signals, etc. on 5 are stored in trace memory 14 in real time, and
When an abnormality is detected by the T circuit 16 or the monitoring processor 11
When the trace operation specified by
Output to.

Monitoring processor 11 as a means of investigating the cause when an abnormality occurs
controls the bus control circuit 17 to read log information stored in the main memory 1722, starts a program for maintenance diagnosis that is pre-installed in the logic device 1, and sends the results via the communication line 19. and output it to the external device 2.

Next, the operation of the monitoring circuit of the logic device of this embodiment configured as described above will be explained.

First, a microprogram that determines the monitoring function of the monitoring circuit 10 is set from the external device t2.

This is done by storing a microprogram from the external device 2 into the local memory 12 via the communication line 19 and the communication adapter 13. This local memo 1
Since the program input to month 2 is made via communication line 19, logic device 1 continues to operate without interrupting normal operation. In the microprogram, optimal monitoring items are set according to the hardware configuration of the logical device 1, which is the monitored device.

When the main processor 21 executes a specific instruction while the logic device 1 is in operation, the WDT circuit 16 is accessed.

On the other hand, when the trace memory control circuit 15 fetches a firmware instruction or accesses the main memory 22,
Address signals, data signals, bus control signals, etc. on the main bus 25 are stored in the trace memory 14 in real time at timings such as when the 10 device groups 23 access. Data storage in the trace memory 14 is performed directly from the main bus 25, and the performance of normal operation of the logic device 1 is not degraded.

If the WDT circuit 16 is not accessed within a certain period of time and an abnormality is detected, the WDT circuit 16
Interrupt 1. In addition, the trace memory control circuit 1
5 stops and causes tracing to the trace memory 14;
The data stored in the trace memory 14 is outputted to the external device 2 via the communication adapter 13 and the communication line 19. The data output of the trace memory 14 is transmitted through the communication line 19.
, and the logic device 1 continues operating without interrupting normal operation.

Note that when the trace operation specified by the monitoring processor 11 ends, the data stored in the trace memory 14 is similarly output to the external device 2 via the communication adapter 13 and the communication line 19.

Further, the monitoring processor 11 controls the bus control circuit 17 to read log information stored in the main memory 22, starts a program for maintenance diagnosis that is pre-installed in the logical device 1, etc. The results are output to the external device 2 via the communication line 19.

〔Effect of the invention〕

As explained above, the present invention enables monitoring functions to be added to an already designed device by directly connecting a monitoring circuit composed of a monitoring processor, local memory, trace memory, communication adapter, etc. to the main bus of the monitored device. In addition to easily strengthening the system, it is possible to investigate the cause of an abnormality by real-time tracing of the main bus at any timing, reading log information in the main memory, and starting a pre-installed maintenance/diagnosis program on the monitored device. It can be executed by programming from an external RW without depending on the main processor, and has the advantage of improving the reliability of the logical device and easily collecting data for investigating the cause of abnormalities.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a logic device as a monitored device including the monitoring circuit shown in FIG. In the figure, 1...Logic device, 2...External device, 10...Monitoring circuit, 11...Monitoring processor, 12...Local memory, 13...Communication adapter, 14...Trace Memory, 15... Trace memory control circuit, 16... WDT circuit, 17... Bus control circuit, 18... Local bus, 19... Communication line, 21... Main processor, 22... - Main memory, 23...I10 device group, 24...Maintenance panel, 25...Main bus.

Claims (1)

[Scope of Claims] A communication means between a processor, a memory and an external device; a programming means for arbitrarily programming a monitoring function via the communication means; and a bus of a monitored device according to the monitoring function programmed by the programming means. a control means for controlling a tracing operation and a maintenance diagnosis operation of the monitored device; and an output means for sending the results of the tracing operation and the maintenance diagnosis operation to an external device via the communication means. Monitoring circuit for logic devices.