JPH08339313A - Logic circuit monitoring device - Google Patents

Abstract

PURPOSE: To change the trigger logic as desired in such a case where the signal of an observation point set in a logic circuit to be monitored (target chip) is acquired as the trace data when the signal of the observation point is turned into a certain type of logic (trigger logic). CONSTITUTION: An FPLA(field programmable logic array) 1 previously produces a logic circuit that satisfies the necessary trigger logic by giving externally the program data PRGI. The observation point data PIN1 to PINn are inputted to the FPLA 1, and the trigger TRG are generated from the FPLA 1 when the trigger logic is satisfied. At the same time, the trace data stored in a memory 2 are shifted to the outside via a shift register 3 and can be observed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring device for a logic circuit, and more particularly to a monitoring device for a plurality of predetermined monitored logic signals in the logic circuit, and when an abnormality is detected, these are detected. The present invention relates to a monitoring device for a logic circuit that stores the state of a monitored logic signal.

[0002]

2. Description of the Related Art As a conventional monitoring device for a logic circuit of this type, there is one having a structure as shown in FIG.
This is the technique disclosed in Japanese Patent Laid-Open No. 221043. The monitoring device 10 includes a monitoring processor 11 that controls the monitoring device 10, a local memory 12 that stores an operation program of the monitoring processor 11, and a communication adapter 13 for communication with an external device (not shown). A trace memory 14 for storing trace data on a main bus 20 which is connected to a logic circuit 21 which is a monitored circuit, and a trace memory control circuit 15 for controlling input / output of data to / from the trace memory 14. , Watchdog timer (W
DT) circuit 16 and a bus control circuit 17 for controlling between the main bus 20 and the local bus 18 of the monitoring device 10.

In such a configuration, the monitor waveforms on the main bus 20 are sequentially stored in the trace memory 14, and when a particular waveform is not monitored within a certain time, the WDT circuit 16 causes the monitor processor to operate. 11 is notified of the abnormality. The monitor processor 11 sends the contents of the trace memory 14 to an external waveform display system via the communication adapter 13 and the communication line 19.

[0004]

In the waveform observing system in such a conventional logic circuit monitoring device, the waveform observing circuit is mounted on the circuit board to observe the waveform on the main bus 20. Therefore, there is a problem that an arbitrary observation point (monitored point) of the waveform observation target cannot be selected.

Further, since the timing for stopping the acquisition of the waveform in the trace memory 14 is generated by the watchdog timer 16 which is generally used, this stop timing is arbitrarily selected with a high degree of freedom. There is also the problem that you cannot do it.

An object of the present invention is to provide a monitoring device for a logic circuit which can improve the degree of freedom in selecting a waveform observation point and trigger logic for waveform observation.

Another object of the present invention is to provide a logic circuit monitoring apparatus which can be mounted on a board of an IC chip on which an observed logic circuit is integrated.

[0008]

According to the present invention, the states of a plurality of predetermined monitored logic signals in a logic circuit are monitored, and when an abnormality is detected, those monitored logic signals at that time are detected. A monitoring device for a logic circuit adapted to store a state of a signal, wherein whether or not a combination of a plurality of monitored logic signals is input and whether a combination of these monitored logic signals matches a predetermined logic. Monitoring of the logic circuit, which includes a logic detecting means for detecting the above logic and a memory means for receiving and storing each of the monitored logic signals at that time in response to the detection of the coincidence of the predetermined logic by the logic detecting means. The device is obtained.

Further, as the logic detecting means, a field programmable logic array in which basic logic gate elements are incorporated in advance and the connection relationship of these basic gate elements can be desirably controlled is used.

[0010]

The logic of the states of the plurality of monitored logic signals to be observed is taken, a trigger signal is generated when the predetermined logic is satisfied, and the states of these monitored logic signals at that time are latched. By using a field programmable logic array that can be derived to the outside and can control the connection relationship of the basic gate elements in the logic section that takes this logic, it is possible to change various waveform observation points and various target points. The monitoring logic circuit can be used freely.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the outline of the present invention. In FIG. 1, FPLA1 is a field programmable logic array, which receives monitored logic signals (observation point data) PIN1 to PINn of a target chip (not shown) to be monitored as an input and instructs sampling of these observation point data. While the signal SMP is active, it is derived while sampling in synchronization with the clock CLK and output as sample data Data1 to Dataan, and the desired logic of these observation point data is taken and when the logic is satisfied, it is triggered to the outside. It has a function of generating the signal TRG.

The configuration of the logic unit for obtaining the desired logic of the observation point data can be changed and controlled as desired by using the programmable characteristics of the field programmable logic array. Therefore, the program enable PRGE and the program data PRGI are supplied, and when the program enable PRGE is active, the program data PRGI is supplied from the outside so that the basic gate element (and Input / output connection relations of gates, OR gates, inverters, D-type flip-flops, etc.) are programmable and controlled to obtain a desired logic of the observation point data of the target chip.

The memory 2 stores the sample data Data1 to Dataan sampled in the FPLA 1 in synchronization with the clock CLK, and shifts the memory data into the shift register 3 when the shift enable SHFEN is active. The shift register 3 receives the data Dout1 to Dout captured from the memory 2 when the shift-out enable SOE is active.
The outn is sequentially shifted in synchronization with the clock CLK and output to the outside as shift-out data SO.

The details of the FPLA 1 will be further described below. FIG. 2 is a functional block diagram of this FPLA1,
An input data sampling unit 110 for sampling the observation point data PIN1 to PINn by the clock CLK while the sampling instruction signal SMP is active, and a logic for inputting the sample data Data1 to Datan and taking a predetermined logic of these input data. It is composed of a function unit 111.

In the logic function unit 111, when the program enable PRGE is active, the input / output connection between the basic gate elements can be freely set according to the program data PRGI supplied serially from the outside. After this logic setting, by inputting the observation point data PIN1 to PINn of the target chip (not shown), the logic operation set in the logic function unit 111 is performed, and when the logic is satisfied, The trigger TRG is generated externally.

FIG. 3 is a block diagram showing a specific example of the logical function unit 111 of FIG. 2, which is composed of a matrix unit 112 and a plurality of function blocks 113-1 to 113-M. The matrix section 112 has inputs / outputs FB00 to FB00 of these function blocks 113-1 to 113-M.
A switch matrix for connecting FB0N, FB10 to FB1N, FBM0 to FBMN to each other as desired. Specifically, as shown in an example of FIG. 6, grid-like wiring and fashion blocks 113-1 to 113-6. Are incorporated in advance, and a desired logic circuit can be obtained by selectively turning on (meaning electrically connecting) each intersection of these grid-like wirings according to program data PRGI from the outside. It is a field programmable logic array IC that can be configured and is widely used.

As an example of the function block 113, as shown in FIG. 4, DF with SR (set / reset)
F40, inverters 41, 42, AND gates 43-4
5, OR gate 46, which is incorporated in advance as shown in the figure.

FIG. 5 shows the trigger logic of the logic function unit 111 for detecting that the pulse width of the signal WR at a certain observation point in the target chip (not shown) has reached a predetermined value and generating the trigger TRG. It is a structural example of a circuit.

The observation point signal WR is fetched into the shift register 116 having a predetermined number of bits in synchronization with the clock signal CLK (operating clock of the target chip), and the respective bit outputs of this shift register 116 are fed to the inverters 117, 119.
Decoding is performed by the OR gate 118 and the NOR gate 120, and the DFF 121 is set by this decoded output, and the trigger TRG is output from the Q output of this DFF 121.

With this logic circuit configuration, the observation point signal WR
When the pulse width of 1 reaches a predetermined value, the DFF 121 is set, the trigger TRG becomes active, and the fact is reported to the outside. By this trigger TRG, an external observation system (not shown) detects that the trigger logic is established, and accordingly, the observation system responds to this by the operation shown in FIG.
The sampling instruction signal SMP shown in (1) is made inactive for the first time, and the shift enable SHFEN is made active so that the data stored in the memory 2 is transferred to the shift register 3.

Then, in synchronization with the clock CLK by the shift-out enable SOE, the data transferred from the memory 2 can be sequentially shifted in the shift register 3 and taken into the observation system as shift-out data SO. is there.

FP for realizing the logic circuit function shown in FIG.
An example of matrix connection of the logical function unit 111 of LA1 is
This is shown in FIG. 6, and shows a state in which the intersections shown by the black circles in FIG. 6 are electrically connected. As shown by these black circles, a method for selectively electrically connecting each crossing portion of the matrix portion is already known, but it will be described with reference to FIGS.

At each intersection X of the matrix portion 112,
A transistor switch 71 as shown in FIG. 7 and a memory cell including a pair of inverters 72 and 73 are provided, and program data PRGI is supplied to this memory cell via a transistor gate 74 including a transistor TR.
Are supplied in synchronization with the clock CLK.

For example, the input program data PR
If GI is "1", this "1" is held by the memory cell, the transistor switch 71 is kept on, and the A line and the B line are electrically connected.

A large number of intersections X are provided as shown in FIG. 6, and which of these intersections is selectively turned on is determined by the logical formula for the observation point data in the target chip as described above. The ON setting control of this intersection is performed before the actual observation.

FIG. 8 is a diagram for explaining an example of the ON setting control of this intersection. Regarding the intersections X # 1 to X # 4, the respective outputs of the transistor gate 74 shown in FIG. 7 are connected so as to propagate serially at the transfer gates TG-1 to TG-3, and these transfer gates TG- are connected.
1 to TG-3 are on / off controlled by an inverted clock of the clock CLK (inverters INV # 1 to # 3).

The preset program data PRGI is serially input from the first-stage transistor gate 74-1 in synchronization with the clock CLK by the number of intersections.
By performing the shift control, the last input data becomes the on / off information of the intersection X # 1 at the first stage.

9 to 10 explain another example for determining the trigger logic of the observation point waveform of the target chip. FIG. 9 shows a normal waveform and an abnormal waveform,
For example, the timings of the RAS (row address strobe) signal and the CAS (column address strobe) signal at the time of normal DRAM access are shown.

In the normal waveform shown in FIG. 9, after the RAS signal falls from the high level to the low level, the specified time C
The AS signal maintains the high level and the RAS signal maintains the low level during that period.

In the abnormal waveform shown in FIG. 9, the CAS signal maintains a high level for a prescribed time after the RAS signal falls, but a high level pulse is generated in the RAS signal during that time. In the case of the trigger logic that detects the abnormal pulse of the RAS signal and generates it as the trigger TRG, the logic function blocks 30 to 33 shown in FIG. 10 are required.

The logic block 31 is a circuit for detecting the fall of the RAS signal, and the logic block 30 is a circuit for detecting the high level of the CAS signal after the fall of the RAS signal. The logic block 32 is a circuit that counts a specified time by using the output of the logic block 30 as a trigger. The logic block 33 detects that the RAS signal is low level based on the output of the logic block 32. At this time, R
When the AS signal goes high, a trigger TRG is generated.

FIG. 11 shows a specific example circuit of each of the logic blocks 30 to 33, which is composed of an AND gate, a NAND gate, a DFF, and a counter, and can be realized by the FPLA shown in FIG.

FIG. 12 is a circuit diagram showing still another example for determining the trigger logic of the observation point waveform of the target chip. For example, in the memory circuit of the target chip, there is a circuit that generates parity from the write data D0 to D7 at the time of writing, and when it is confirmed whether this parity generating circuit is operating normally, these write data D0 to D7 are used. A parity generation circuit 34 for generating a parity P by inputting is input, and the parity data PARITY from the output P and the parity generation circuit in the target chip is provided.
When the write signal WR is active, and are compared by the exclusive OR (EXOR) gate 35 to determine a match. If they do not match, a non-matching trigger TRG is generated from the Q output of the DFF 36.

The trigger logic function shown in FIG.
It can be easily realized by PLA.

FIG. 13 is a block diagram showing an example of use of the present invention. It is assumed that the target chip 21 for waveform observation and the logic sample LSI 22 shown in FIG. 1 are connected by a wiring pattern on a circuit board. . When the target chip 21 is a narrow-pitch package, the logic sample LSI 22 is mounted on the package in advance so that the waveform trace during debugging can be easily performed.

The waveform observation system 23 and the logic sample LSI 22 are connected by a cable or the like. The waveform observation system 23 obtains a predetermined trigger logic function by supplying the necessary trigger logic to the FPLA in the logic sample LSI 22 by using the program enable PRGE and the program data PRGI as described above.

After that, the waveform of the target chip 21 is observed, and it is known that the trigger logic is established in response to the generation of the trigger TRG, and the shift enable SHFEN,
The shift-out enable SOE is supplied to sequentially read the trace data from the shift register (FIG. 1) and display it on the display unit.

FIG. 14 is a block diagram showing another example of use of the present invention, which is an example in which the logic sample LSI 22 is incorporated in the waveform observation system 23. The target chip 21 is connected to the logic sample LSI 22 in the waveform observation system 23 via the connector 24 and the cable 25.

FIG. 15 shows still another example of the use example of the present invention. The timing of waveform observation is generated by the target chip 21, and the trigger logic is realized by the logic sample LSI 22. When the trigger TRG is generated, the high performance oscilloscope 26 can observe a desired waveform of another target chip 27 via the probe 28 using the trigger TRG as an external trigger.

[0041]

As described above, according to the present invention, since the logic sample LSI is composed of the FPLA, the memory, and the shift register, one LSI can be realized, and any observation of the target chip is possible. The effect is that points can be selected.

Further, by forming the trigger logic in FPLA, the trigger logic can be freely formed, and the versatility is extremely high.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of FPLA1 in FIG.

3 is a block diagram showing an example of a logical function unit 111 in FIG.

FIG. 4 is a block diagram showing an example of a function block 113 in FIG.

FIG. 5 is a diagram showing an example of trigger logic of a logic function unit 111 of the FPLA1.

FIG. 6 is a diagram showing a connection example of a logical function unit 111 of the FPLA1.

FIG. 7 is a diagram showing an example of a matrix section of a logical function section 111 of the FPLA1.

FIG. 8 is a circuit diagram for programming a matrix portion.

FIG. 9 is a waveform diagram showing an example of a trigger logic.

10 is a block diagram for satisfying the trigger logic of FIG.

11 is a specific circuit diagram of the block of FIG.

FIG. 12 is a block diagram showing another example of trigger logic.

FIG. 13 is a diagram showing an example of a mode of use of the embodiment of the present invention.

FIG. 14 is a diagram showing another example of usage of the embodiment of the present invention.

FIG. 15 is a diagram showing another example of usage of the embodiment of the present invention.

FIG. 16 is a diagram showing a conventional circuit example for waveform observation.

[Explanation of symbols]

1 FPLA (Field Programmable Logic Array) 2 Memory 3 Shift Register 21, 28 Target Chip 22 Logic Sample LSI 23 Waveform Observation System 24 Connector 25 Cable 26 Oscilloscope 27 Probe 110 Input Data Sample Section 111 Logic Configuration Section 112 Matrix Section 113-1 ~ 113-M function block

Claims (5)

[Claims] 1. A logic for monitoring the states of a plurality of predetermined monitored logic signals in a logic circuit and storing the states of these monitored logic signals at the time when an abnormality is detected. A circuit monitoring device, which receives a plurality of monitored logic signals as input, and detects whether or not a combination of these monitored logic signals matches a predetermined logic, and the logic detection means. A monitoring device for a logic circuit, comprising: storage means for receiving and storing each of the monitored logic signals at that time in response to detection of coincidence of a predetermined logic by the detection means. 2. The logic according to claim 1, wherein the logic detecting means is a field programmable logic array in which basic logic gate elements are incorporated in advance and the connection relationship of these basic gate elements can be controlled as desired. Circuit monitoring equipment. 3. A logic gate circuit which controls the connection relationship of the basic gate elements by external program data and receives each of the monitored logic signals as an input and which satisfies the predetermined logic. The monitoring device for a logic circuit according to claim 2, wherein 4. The memory means constantly writes and stores each of the monitored logic signals, and stops the write operation of the memory in response to the coincidence detection by the logic detection means and stops the write operation at that time. 4. The logic circuit monitoring device according to claim 1, further comprising an output unit that outputs the contents of the memory to the outside. 5. The logic circuit monitoring device according to claim 4, wherein said output means is a shift register which takes in the contents of said memory and sequentially shifts and outputs the contents to the outside.