KR100728943B1 - A semiconductor memory device with self test mode - Google Patents

Abstract

There is provided a semiconductor memory device capable of determining a memory defect by internally testing itself without making a memory access pin externally. The semiconductor memory device according to the present invention includes a clock generator, an address signal generator, a self test controller, and a comparator. First, the clock generator generates a clock of a predetermined period in the self test mode and provides the clock signal to a counter constituting the address signal generator and the self test controller. The self-test control section controls the main memory to write "0" in all positions of the main memory and read it again, and then write "1" and then read it. The comparator determines whether the data read from the main memory is the same as the data originally written to the main memory, and generates a signal indicating this if it is not the same.

Self Test, Memory Fault, Clock Generator, Counter, Main Memory

Description

A SEMICONDUCTOR MEMORY DEVICE WITH SELF TEST MODE}

1 is a block diagram illustrating a configuration of the present invention.

2 is a circuit diagram of one embodiment of the present invention.

3 is a circuit diagram of a latch according to the present invention.

4 is a signal waveform diagram for the circuit shown in FIG.

[Description of Reference Symbol in Drawing]

101: clock generator 103: address signal generator

105: self-test control unit 107: main memory

109: comparator STE: self test enable signal

CA: counter address signal W: drive control signal

SWE: Self-Write Enable Signal SRE: Self-Read Enable Signal

SOE: Self Output Enable Signal SDIN: Self Input Data Signal

MA: Main address signal MWE: Main write enable signal

MOE: Main output enable signal MDIN: Main input data signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a self test mode, and more particularly, to a semiconductor memory device capable of performing a memory test without a memory tester.

In the conventional embedded RAM, a method of determining whether there is a memory defect includes a method of determining whether a main chip is normally operating or not, and determining whether a memory is abnormal, and an input pin of a memory part in an embedded RAM. There is a method of directly testing a memory defect using a test device made on a main chip, and a method of inputting a memory address and comparing data using a scan chain. In the conventional method, when the external input pin is used, not only the chip size is increased but also a memory-only test apparatus is required. The method of testing the entire chip without testing the memory has a problem that it is impossible to determine whether the memory is defective. In addition, the method using the scan chain has a problem of using a logic test device for logic and control for memory test.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor memory device capable of determining a memory defect by internally testing a memory without making a memory access pin.

Another object of the present invention is to provide a semiconductor memory device capable of determining whether a memory is defective without a memory test device.                         

Another object of the present invention is to provide a semiconductor memory device having a structure capable of determining whether a memory defect is present in an embedded RAM, which is difficult to test by a conventional method.

In order to achieve the above object, the present invention provides a semiconductor memory device having a self-test mode, comprising: a clock generator for generating a clock of a predetermined period in the self-test mode, a main memory for storing data, and a clock generation; An address signal generator for sequentially generating an address signal of the main memory by receiving a negative clock, a self-test controller for controlling the main memory to write predetermined data to or read data from the main memory according to the address signal; And a comparing section for determining whether the read data is the same as the recorded data.

The address signal generator is a counter that sequentially receives a clock of the clock generator. The self-test control section selectively or sequentially reads 0 and writes 1 and then writes 1 to all positions of the main memory.

In addition, the present invention is a semiconductor memory device having a self test mode, a clock generator for generating a clock of a predetermined period in the self test mode, and a main memory for storing data (a a self test controller which receives the clock generated from the clock generator in the self test mode, and generates an address signal, a drive control signal, and an input data signal for the main memory; An address that receives an address signal and a main address signal from the test controller and provides a self address signal in the self test mode and a main address signal in the normal mode to the address input terminal of the main memory. An latch and an input data signal and a main data signal from the self test controller A write data latch for inputting a self data signal in the self test mode, and a main data signal in the normal memory mode to the data input terminal of the main memory section; a drive control signal from the self test control section; A driving signal latch for receiving the main drive signal and outputting the self drive signal in the self test mode in the self test mode, and the main drive signal to the drive signal input terminal in the main memory in the normal mode, and in the self test mode. And a comparator for determining whether or not the data signal provided in the write data latch unit and stored in the main memory unit is the same as the self input data signal originally provided in the write data latch unit.

The latch unit includes a first transmission gate for transmitting a signal from the self-test controller to the main memory in the test mode, and a second transmission for transmitting the main signal to the main memory in the normal mode. A plurality of latch circuits including gates are provided. When the main memory stores N (= 2 ⁿ ) data of M bits, the lower n bits of the outputs of the counters constituting the address signal generator and the self test controller correspond to the address signals, and n + The first bit corresponds to the drive control signal, and the n + 2 th bit corresponds to the input data signal. The drive signal latch unit is composed of a write enable latch circuit, a read enable latch circuit, and a memory output enable latch circuit. The comparator includes a logical sum gate for performing an OR operation on an M bit data signal output from the main memory, and an AND gate for performing an AND operation on the M bit data signal output from the main memory.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

First, Figure 1 is a block diagram illustrating the configuration of the present invention. As shown in FIG. 1, a semiconductor memory device according to the present invention includes a clock generator 101, an address signal generator 103, a self test controller 105, a main memory 107, and a comparator 109. Doing. In FIG. 1, STE denotes a self test enable signal, CLK denotes a clock signal generated from the clock generator 101, CA denotes a counter address, and W denotes a memory control signal. control signal, MOUT indicates a memory output signal, and ERR indicates a memory fault determination signal, respectively.

In FIG. 1, when the self test enable signal STE is input, that is, the clock generator 101 generates the clock CLK of a predetermined period in the self test mode. The address signal generator 103 receives the clock of the clock generator 101 and generates an address signal CA of the main memory 107 that stores data. The address signal generator 103 may be implemented as a counter that receives a clock of the clock generator 101 and sequentially increases its value. The self test control section 105 provides the memory control signal W to the main memory 107, whereby predetermined data, for example, all of the data is stored in the main memory 107 in accordance with the address signal generated from the address signal generating section 103. After 0 or all 1s are written, the main memory 107 is controlled to be read back from the main memory 107. In addition, the self-test control unit 105 writes and reads 0 at all positions of the main memory 107 and then writes and reads 1 at all positions again, or writes and reads 1 first and then writes and reads 0 at the next. The main memory 107 can be controlled. The comparison unit 109 determines whether the data MOUT read out from the main memory 107 is identical to the data originally recorded in the main memory 105 under the control of the self test control unit 105. If the comparison result is not the same, a memory defect determination signal ERR having a predetermined level is generated.

2 is a circuit diagram of an embodiment of the present invention. As shown in FIG. 2, the semiconductor memory device having the self test mode according to the present embodiment includes a counter 203 constituting a clock generator 201, an address signal generator, and a self test controller. An address latch unit 205, a drive signal latch unit 207, an input data latch unit 209, a main memory 211, and a comparison unit 213 are provided. First, the clock generator 201 generates the clock CLK for a predetermined period when the self test enable signal STE is activated in the self test mode. The counter 203 receives the clock CLK generated from the clock generator 210 in the self test mode and performs clock counting. The lower four bits 215 of the counter 203 are stored in the main memory 211. The upper two bits 217 correspond to the drive control signal W0 and the input data signal W1, respectively. This embodiment assumes that the address of the main memory 211 is 4 bits and the input data is 4 bits. In general, when the main memory 211 stores N (= 2 ⁿ ) data of M bits, the lower n bits of the output of the counter 203 constituting the self test controller correspond to an address signal, and the n + 1 th The bit corresponds to the driving signal, and the n + 2 th bit corresponds to the data signal. In other words, the lower n bits of the counter 203 constitute the address signal generator 103 as the address counter 215, and the upper two bits constitute the self test controller 105 as the control counter 217.

The counter address CA0 generated by the counter 203 is input to the latch circuit 219a. The latch circuit 219a outputs the counter address CA0 to the address input terminal of the main memory 211 in the self test mode. In the normal mode, however, the main address MA0 is output to the address input terminal of the main memory 211. When the driving control signal W0 generated by the counter 203 is input to the driving signal latch unit 207, the main memory 211 driving signals SWE, SRE, and SOE are generated through the inverters INV1 and INV2. These drive signals are input to the latch circuits 221a, 221b, and 221c, respectively. Here, SWE is a self write enable signal, SRE is a self read enable signal, and SOE is a self output enable signal. (W1, W0) = (0, 0) while (CA0, CA1, CA2, CA3) changes from (0, 0, 0, 0) to (1, 1, 1, 1) sequentially in the self test mode If SWE = 1, SRE = 0, SOE = 1, and SDIN = 0, data "0" is written to all positions of the main memory 211. If (W1, W0) = (0, 1), SWE = 0, SRE = 1, SOE = 1, and therefore data is read from all positions of the main memory 211. If (W1, W0) = (1, 0), SWE = 1, SRE = 0, SOE = 0, and SDIN = 1, so data "1" is written to all positions of the main memory 211, and (W1, W0) If = (1, 1), data are read from all positions of the main memory 211. Since (W1, W0) correspond to the upper bits of the output of the counter 203, the counter 203 reads after writing the data " 0 " in all positions of the main memory 211 in the self test mode, and then reads the data again. The process of reading after writing " 1 " is performed in the main memory 211. FIG.

In the self test mode, the latch circuits 221a, 221b, and 221c output the control signals SWE, SRE, and SOE generated from the drive control signal W0 to the drive signal input terminal of the main memory 211. The main write enable signal MWE, the main read enable signal MRE, and the main output enable signal MOE are output to the drive signal input terminal of the main memory 211, respectively. The input data signal W1 generated from the counter 203 is input to the latch portion 209 for the data signal, and the data signal W1 is input to four latches 223a, 223b, and 223c via the inverters INV3 and INV4. , 223d). The four latches 223a, 223b, 223c, and 223d output the data signal SDIN via the inverters INV3 and INV4 to the data signal input terminal of the main memory 211 in the self test mode. In this case, the main input data signals MDIN0 to MDIN3 are output to the data signal input terminals of the main memory 211, respectively.

The comparator 213 includes a NOR gate NOR1 for performing a NOR operation on each bit of the output signals Mout0 to Mout3 from the main memory 211, and a NAND gate NAND1 for performing a NAND operation. Doing. The output of the NOR gate NOR1 is controlled by the transfer gate M3 and the transfer gate M3 is W0 = 1 (SWE = 0, SRE = 1, SOE = 1) in the self test mode (STE = 1). When W1 = 0, the output of the NOR gate NOR1 is transferred to the comparator output terminal ERR. That is, when the self test control signal is (W1, W0) = (0, 1), the process of reading data "0" recorded in all positions of the main memory 211 at (W1, W0) = (0, 0) As a counter, the NOR gate NOR1 outputs "0" when any bit of the output signal of the main memory 211 is "1", and finally outputs "1" through the output terminal ERR. This indicates that there is a defect in the location of the main memory 211 corresponding to the lower 4 bits CA0 to CA3. Similarly, the output of the NAND gate NAND1 is controlled by the transfer gate M4, and the transfer gate M4 outputs the output of the NAND1 output terminal when (W1, W0) = (1, 1) in the self test mode. Pass to (ERR). If the self test control signal reads data " 1 " written in all positions of the main memory 211 at (W1, W0) = (1, 0), the defect of the memory is (W1, W0) = (1, 1). As a process of determining, NAND1 outputs "1" even if any one bit of the output signal of the main memory is "0", and thus outputs "1" through the output terminal ERR, thereby presenting the current of the main memory 211. The location will be alerted.

A detailed circuit diagram for the latch circuit 219a is shown in FIG. As shown in FIG. 3, the latch circuit 219a includes a first transfer gate M1 for transmitting the signal CA0 from the counter 203 to the main memory 211 in the self test mode, and the normal mode. A second transfer gate M2 for transmitting the main signal MA0 to the main memory 211 is provided.

A detailed operation of the embodiment of the present invention shown in FIG. 2 will be described with reference to FIG. 4. 4 is a signal waveform diagram for the circuit shown in FIG. When STE is "0", the clock generator 201 and the counter 203 do not operate, so the clock signal CLK is "0", and the output signals CA0 to CA3, W0 and W1 of the counter 203 All bits are initialized to have "1". Since the self-test enable signal STE is "0" in the address latch unit 205, the transfer gate M1 is turned off and the transfer gate M2 is turned on so that the main addresses MA0 to MA3 are turned off. It is input to the main memory 211. The main inputs MWE, MRE, MOE, MDIN0 to MDIN3 are inputted to the main memory 211 in the same manner as the drive signal latch portion 207 and the input data latch portion 209, and the self test does not operate. In the comparator 213, if the STE is "0", the NMOSFETs N1 and N2 are turned on, and the nodes Lcheck and Hcheck are "0", and the comparator output terminal ERR is always "0". In addition, since the nodes Hcon and Lcon become "1", the output signal Mout of the main memory 211 is not transmitted.

On the other hand, when the self test enable signal STE is "1", the clock generator 201 is turned on to generate the clock signal CLK having a constant pulse width. The clock signal CLK generated at this time is input to the counter 203. The address to the main memory is sequentially generated by the clock signal CLK counting by the counter 203, and the control signals W1 and W0 for controlling the driving and input data of the main memory are sequentially generated. It takes the output and is generated sequentially. Since the control signal is composed of two bits, W0 and W1, four cycles exist in the address counter 215.                     

A. When (W1, W0) = (0, 0)

The self write enable signal SWE becomes " 1 " to become a write cycle. At this time, since the self test enable signal STE is "1", the main write enable signal MWE is not input. The self-read enable signal SRE becomes " 0 ", which is a write disable state, and the self-output enable signal SOE is also in the same state. The self input data SDIN becomes "0" and "0" is input to all addresses. Since the nodes Lcon and Hcon are "1", the transfer gates M3 and M4 are turned off so that the nodes Lcheck and Hcheck maintain the initial value "0". Therefore, the comparator output terminal ERR is kept at "1".

B. When (W1, W0) = (0, 1)

The self write enable signal SWE is " 0 ", the self write enable signal SRE is " 1 ", and the self output enable signal SOE is " 1 " The node Lcon becomes " 0 " so that the transmission gate M3 is enabled. Since the node Hcon is "1", the transmission gate M4 is turned off. When the outputs Mout <0: 3> of the main memory are all "0", the output of the NOR gate NOR1 is "1", and the node Lcheck is constantly "0", and the output terminal ERR is Will remain "0". However, if any one of the outputs Mout <0: 3> of the main memory is "1", the output of the NOR gate NOR1 becomes "0" and the node Lcheck becomes "1". 1 "is output to indicate a memory defect.

C. When (W1, W0) = (1, 0)

The self write enable signal SWE is " 1 ", and the self read enable signal SRE and the self output enable signal SOE are " 0 " to enter the write mode. The node Lcon becomes " 1 " so that the transmission gate M3 is disabled. Node Hcon also becomes " 1 " so that transmission gate M4 is disabled. At this time, the self input data SDIN becomes "1", and data "1" is recorded in all positions of the main memory 211.

D. When (W1, W0) = (1, 1)

The self write enable signal SWE is " 0 " and the self read enable signal SRE and the self output enable signal SOE are " 1 " to enter the read mode. The node Lcon becomes " 1 " so that the transmission gate M3 is disabled. The node Hcon becomes " 0 " so that the transmission gate M4 is enabled. When the outputs Mout <0: 3> of the main memory 211 are all "1", the output of the NAND gate NAND1 is "0", and the node Hcheck is constantly "0" and the comparator ( The output terminal ERR of 213 holds " 0 ". However, when "0" occurs in any one of the outputs Mout <0: 3> of the main memory 211, the output of the NAND gate NAND1 becomes "1" and the node Lcheck becomes "1", and the comparison is made. The output terminal ERR of the unit 213 becomes "1" to indicate that there is a memory defect.

Table 1 below is a truth table when the memory is not defective, and Table 2 is a truth table when the memory is defective.

STE W1 W0 CA3 CA2 CA1 CA0 ERR mode 0 X X X X X X 0 main One 0 0 X X X X 0 Test (0 records) One 0 One X X X X 0 Test (0 reads) One One 0 X X X X 0 Test (1 record) One One One X X X X 0 Test (1 read)

STE W1 W0 CA3 CA2 CA1 CA0 ERR mode 0 X X X X X X 0 main One 0 0 X X X X 0 Test (0 records) One 0 One X X X X One Test (0 reads) One One 0 X X X X One Test (1 record) One One One X X X X One Test (1 read)

As shown in Table 2, if the memory is defective, (STE, W1, W0) = (1, 0, 1) and (STE, W1, W0) = (1, 1, 1) The output terminal ERR of the comparing unit 213 outputs "1" to indicate that the memory is defective.

What has been described so far is for the embodiments of the invention and is not intended to limit the scope of the invention. Therefore, various changes or modifications to the above-described configuration are possible at the level of those skilled in the art. The scope of the invention is defined in principle by the claims that follow.

According to the present invention, it is possible to determine whether there is a memory defect by internally testing itself without making a memory access pin. In addition, it is possible to determine whether a memory is defective without a memory test device, and there is an advantage that a memory defect may be determined even in an embedded RAM having a difficult memory test by a conventional method.

Claims (8)

In a semiconductor memory device having a self test mode, A clock generator which generates a clock of a predetermined period in the self test mode; Main memory for storing data, An address signal generator which receives the clock of the clock generator and sequentially generates an address signal of the main memory; A self test controller for controlling the main memory such that predetermined data is written to or read from the main memory according to the address signal; A comparison section for determining whether the read data is the same as the recorded data A semiconductor memory device comprising: a. The method of claim 1, And the address signal generator is a counter that sequentially receives a clock of the clock generator. The method of claim 1, And the self-test control unit selectively or sequentially reads 0s at all positions of the main memory and reads the 1s at all positions of the main memory. In a semiconductor memory device having a self test mode, A clock generator for generating a predetermined cycle clock in the self-test mode; A main memory for storing data; A self test controller which receives the clock generated from the clock generator in the self test mode and generates an address signal, a drive control signal, and an input data signal for the main memory; (4) Input the address signal and the main address signal (normal address signal) from the self test controller and input the self address signal in the self test mode and the main address signal in the normal mode in the normal mode. An address latch provided to the terminal, ⑤ A write data latch for receiving an input data signal and a main data signal from the self test controller and providing the self data signal in a self test mode and the main data signal in a normal mode to a data input terminal of the main memory unit. A write data latch, ⑥ A drive that receives the drive control signal and the main drive signal from the self test controller and outputs the self drive signal in the self test mode and the main drive signal in the normal mode to the drive signal input terminal of the main memory. A driving signal latch, A comparator for determining whether a data signal provided to the write data latch unit in the self test mode and stored in the main memory unit and read out is the same as a self input data signal originally provided to the write data latch unit; A semiconductor memory device comprising: The method of claim 4, wherein The latch portion includes a plurality of latch circuits, The latch circuit A first transmission gate for transmitting a signal from the self test controller to the main memory in a test mode; A second transmission gate for transmitting the main signal to the main memory in a normal mode; Semiconductor memory device comprising a. The method of claim 4, wherein The main memory stores N (= 2 ⁿ ) M bits of data, The self test controller is composed of one counter, The lower n bits of the output of the counter correspond to an address signal, the n + 1 th bit corresponds to a drive control signal, and the n + 2 th bit corresponds to an input data signal. The method of claim 4, wherein The drive signal latch unit includes a write enable latch circuit, a read enable latch circuit, and a memory output enable latch circuit. A semiconductor memory device characterized by the above-mentioned. The method of claim 4, wherein The comparison unit A first logic gate performing an OR operation on an M bit data signal output from the main memory; A second logic gate performing an AND operation on the M-bit data signal output from the main memory A semiconductor memory device comprising: a.

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