JPS5860363A - Operation hysteresis storing system for logical device - Google Patents

Abstract

PURPOSE:To completely collect information required for searching troubles in a logical device by incorporating operation hysteresis storing means for the logical devices into plural packages constituting the logical device. CONSTITUTION:Packages 1-4 executing independent logical operation are respectively provided with logical circuits 5-8 and logical operation hysteresis storing and controlling circuits 9-12, and a control part 13 for controlling the operation of all the storing and controlling circuits 9-12 is incorporated in the package 4. Each of the circuits 9-12 is provided with a storage circuit successively storing information in each package synchronously with an operation cycle on the basis of a logging command and a shift register reading out the information stored in said storage circuit. The logical circuit 8 in the package 4 is provided with an event detecting circuit, which informs an even such as error generation in each package during the execution of processing to the control part 13 and an output device 14. Receiving the information, the device 14 outputs a command to the control part 13 to set up the information stored in the circuts 9-12 of respective packages in their registers and output the set information to the device 14 in series.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an operation history method for a logical device. Regarding the method.

In recent years, information processing devices have become more sophisticated, complex, and faster, and the causes of failures in logical devices have also become more diverse. This makes it extremely difficult to test the logic device or analyze errors when a failure occurs.

On the other hand, a means for storing the operation history of the logical device called a tracer is added to the logical device, and this tracer stores the operation history of the logical device, such as the execution program address, main memory address, register, and 7-lip flop values. Attempts have been made to facilitate error analysis by sequentially storing the status, stopping the storage at the point of occurrence, and outputting the stored information.

Error analysis using this trainer allows you to know past status information in order to search for the cause of the error when the hardware design and construction are identified. It has the advantage of being able to shorten the time for error analysis (as well as reducing the number of errors with unknown causes that are corrected).

The conventional operation history method for logic devices is to provide an operation history storage circuit concentrated in one place for the logic circuits constituting the logic device, and connect nine necessary signals from the logic circuits to this. The operating state of the logic device is memorized at appropriate timing, and the logic device stops the memory operation when a pre-instructed event such as an error occurs, and outputs the memory information of the operation history memory circuit at the necessary time. The main purpose is to know the operation history of the logical device.

In this way, in the conventional logical device operation slow history storage method, the operation history storage circuit is concentrated in one place. It is necessary to connect signals from the logic circuit to the memory circuit, and a large number of connection wires are required between the package in which the logic circuit is mounted and the package in which the memory circuit is mounted. In addition to this, there is a drawback that the logic circuit delay δ increases as the line length of the logic circuit fan-out increases, or the number of unaudio gates increases by 7 in order to reduce the logic circuit delay. In addition, as the degree of integration of devices increases, the logic circuits implemented in one package become more complex and large in number, and a large number of main output bins of each package are used. It may be impossible to output logic signals that are closed outside the package, and it is necessary to record the operation history of circuits that increase or decrease depending on the system configuration of the information processing system, such as input/output channel circuits. There was a drawback that if the input/output channel O (No. 1), which is not stored, is also connected to the storage circuit, it becomes t and meaningless information is stored unconditionally.

The purpose of the present invention is to create a system in which sufficient information necessary for fault detection can be obtained, that is, to alleviate the restrictions on the number of people in the package, to suppress the increase in circuit delay in logic circuits, and to eliminate unnecessary information in circuits that can be separated. An object of the present invention is to provide an operation history storage method for a logical device that enables control without storage.

In order to achieve the above object, the operation history storage method for a logic device according to the present invention stores package information based on a logging instruction in the operation cycle for each device storage package that is composed of packages that perform a plurality of independent logical operations. An operation history storage means for sequentially storing information in synchronization with the operation history storage means, a register for outputting the information stored in the operation history storage means, and a control unit for centrally controlling the operation history storage means and the register are provided. When such an event occurs, the information in each operation history storage means is set in each of the registers, and the set information is serially read out to an external output device.

According to the above configuration, the number of operation history control signals connected to each package is reduced, and the amount of nodeware is also minimized. Furthermore, since the memory circuit can be set in accordance with the logic size, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained with reference to the drawings.
4 is a package that constitutes a logic device; 5, 6, 7, and 8 are logic circuits that perform the original logical operation of the logic device; 9, 10
, 11 and 12 are logic operation history storage control circuits of the respective logic circuits, 13 is a circuit that controls the operation of all storage control circuits, and 14 is a circuit that controls the control section 13.'! Figure 2, which shows a device that outputs information stored in the I-memory control circuit, shows the details of nodes 1, 2 and 3 in Figure 1. This is a diagram showing 1. 5 is the same logic circuit as in Fig. 1 ~ addition is a memory circuit,
The address designation circuit of the storage circuit has a 21m+x counting function, and the feather represents a register that is a readout register of the storage circuit area and also operates as a shift register.

FIG. 3 is a diagram showing the details of the package 4 in FIG. They are different in that they have Also, logic circuit 8#
has a special event detection circuit 33. 12 is the first
The same logical operation history storage control circuit as shown in the figure, 30 is a storage control circuit connected to each package, a storage circuit for writing that data, 31 is an address register of the storage circuit, which has a +1ij count function. 32 is the logical operation of each package; the memory control circuit and circuit 30.3;
1 represents a circuit that controls 1. Note that the address designation circuit 4 shown in FIG. 2 is included in the storage control circuit 12 shown in FIG.
In addition to the memory circuit, the corresponding circuit is also included, but it is omitted in this figure.In this logic device, the packages 1.2.3.4 are connected by means of connecting the packages, such as backboard wiring. Necessary processing is executed by instructions or commands given from the outside. 101.1 in Figure 1
02.103.104.105.106.107.10
Reference numeral 8 denotes a connection line that logically connects each package and controls an interface with an external device.

When the logical device is given instructions or commands one by one, it executes processing accordingly. During this processing, based on the logging command 121 given from the logic device to the control circuit 32, the -circuit 32 is set to address color/) [113-1, write permission signal line 113-2, all enabled. The memory circuit 20 logs necessary input/output information and status information of the logic circuit 5 via the data line 109. This operation is performed in the same way for all paraphrases.

Note that the details of the logging operation are generally expressed in a known manner and will not be described here.

On the other hand, when an event such as a predetermined error occurs during the execution of the processing, the event detection circuit 33 operates and the signal line 1
20 to report the occurrence of the event to the Cape Circuit. The control circuit 32 performs an address call based on the event occurrence report).
$1113-1, the write permission signal line 113-2 is disabled, and the logging operation to the memory circuit is stopped. This operation is performed similarly for all packages.

The above-mentioned event occurrence report is also made to the output device using a known general method.

The output device 14 receives the event occurrence report, and when it recognizes it, issues a logging content output command to the control circuit through the signal line 118-1.

The control circuit section operates as follows in response to this logging content output command.

First, enable the signal line 1\-1 to 5, advance the clock by 1 clock, and change the value of the address register 21 to +IK,
L: Specify the address to the oldest memory circuit address from the time when the event occurred.

Next, this address is designated and the signal line 113-3 is set to logic 0 to advance one clock in order to load the contents of the nine memory circuit 20 into the register n through the data line 201. This operation is performed simultaneously for all packages using the same procedure. After that, the address register 31 is connected to the signal line 301.
is enabled and set to O value, and then the signal line 212 is enabled to permit data writing from the data line i1a to the memory circuit (support). On the other hand, the data line 114 is connected to the memory circuit 20
The read L register 22 of the data line 114.115.116.117.1111 operates as a shift register.
and use the logical O to shift in the logical O data.
K is given. Naturally, the number of words of the memory circuit (material) is equal to or larger than the number of bits of the shift register of the entire package when the read register is used as a shift register.

In the above state, by setting the signal line 113-3 to logic 1 and shifting the successive registers, the data line 1
KL sets the 160 input to the least significant bit and outputs data from the most significant bit to the data line 117, and all packages are in that state.

Then, the clock is passed until the carry signal 303 is output from the most significant bit from the address register 31, and
The contents of the read register of the operation history storage control circuit of each package are stored in the storage circuit 30. The completion of this shift operation is reported to the output device 14 through the signal line 118-2, and in response, the output device 14 issues an output command to the control circuit 32 through the signal line 118-3.

In response to this output command, the control circuit 32 further operates as follows.

First, a logic 1 is set in the data line 114, and then the Shinshu line 212 is disabled and writing to the memory circuit (9) is prohibited.
The memory circuit 30 is made read-only.

At this time, the address register is OK.

The output of the memory circuit (material) is connected to the output device 14 through a data line 119, and the contents of the memory circuit 3 are read every time the value of the address register 31 changes (signal line 113-3 is set to logic IK). It's starting to go well.
On the other hand, the control circuit 32 performs the same control as the shift operation, and performs the shift operation and data transfer to the output device until the data line 118 becomes logic 1. data line 1
18 becomes logic 1, it reports the completion of data transfer to the output device 14 through the signal line 118-2, and the signal line 113-
3 to logic 0 terminates the shish7 operation. ' With the above operations, the operation history memory circuit of each package, 11
The contents of the word are transferred to the output device 14.

By repeatedly performing these operations, the contents of all words can be output to the output device.

This embodiment is effective in that the input/output pins of the package can be used for signals necessary for the original logic operation of the logic device, since the number of signals for controlling the operation history connected to each package is minimized. .

Further, since the operation history circuits distributed to each package are centrally controlled in one place, there is an advantage that the increase in the number of windows can be kept to a minimum.

Furthermore, in the configuration shown in FIG. 1, if the package 2 is made into a circuit that can be separated, for example, if the data lines 115 and 116 are connected with a dummy package etc., the same operation can be achieved without any influence on other circuits. There is also the advantage that no extra memory circuit is required since the oscillator is more powerful.

As described in detail above, the present invention provides a means for storing the operation history of a logical device for each of a plurality of packages constituting the logical device. This has the advantage that the information operation history can be stored while minimizing restrictions on package input/output pins and logic circuit delay.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the operation history storage method of a logical device according to the present invention, FIG. 2 is a detailed block diagram of packages 1.2.3 in FIG. 1, and FIG. 3 is the same as in FIG. 1. It is a detailed configuration diagram of the package 4 in FIG. 1.2.3.4 - Logic circuits that make up the logic device 5.6.7.8 Logic circuit that performs the original operation of the logic device 9.10.11.12 - Operation history storage Control circuit-13
...Control unit 14--To output device 2 30-Storage circuit 21.31--Address register. 22-・Read register 32-Control circuit Patent applicant NEC Corporation

Claims (1)

[Scope of Claims] In a system comprising a device composed of a plurality of packages that perform independent logical operations, an operation history storage that sequentially stores package information in synchronization with an operation cycle based on a logging command for each package. means and a register for outputting the information stored in the operation history storage means, further provided with a control unit number for centrally controlling the operation history storage means and the register, when an event such as an error occurs, setting information in each operation history storage means in each of the registers;
A system for storing an activation history of a logic device, characterized in that the set information is serially read out to an external output device.