JPS5935456B2 - arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an improvement of an arithmetic processing device having two arithmetic units.

[Background of the invention]

In arithmetic processing devices that require high reliability, in order to detect calculation errors in the arithmetic units used in the arithmetic operations, two sides of the same arithmetic unit are provided, and the arithmetic units on the two sides are made to perform the same arithmetic operation. , compare the calculation results, and if they match, it is assumed that the specified calculation was performed correctly; if they do not match, it is assumed that a calculation error has occurred, and an error signal is sent to the control device, The control device is performing some kind of error handling.

In this case, the arithmetic units on the two sides are generally configured to perform the same operation in a fixed manner, and even if an error occurs, it is difficult to tell whether it is a malfunction in the arithmetic unit or in the comparator circuit. Ta. For this reason, a method has been proposed for checking the normality of the comparator circuit by independently controlling the computing units on the two sides, giving the same data to each computing unit, and having them perform different operations (Japanese Patent Application Laid-Open No. No. 51-48241). However, in this conventional method, correct normality check of the comparator circuit is guaranteed only when the arithmetic units on the two sides operate correctly, and is not sufficient in terms of reliability. [Object of the Invention] An object of the present invention is to provide a means for correctly dividing whether an error is in the arithmetic unit or in a comparator circuit with respect to error processing when an arithmetic error is detected in an arithmetic processing device having two arithmetic units. It is about giving.

[Summary of the invention]

The feature of the present invention is that by realizing the function of individually importing the calculation results output from the calculation units of the two sides into the calculation result storage register, the two sides of the calculation can be stored in the register group where the calculation results are stored. By storing the operation results of the units separately and referring to the operation results of the two register groups, it is possible to easily determine what operation each operation unit has performed.

[Embodiments of the invention]

The figure shows a block diagram of an embodiment of an arithmetic processing device according to the present invention.

In the figure, the arithmetic unit 3 and the arithmetic unit (B) 4 are connected to the register 1, the register (B) 2, the gate 10, and the comparison circuit 8, respectively, and the arithmetic unit (A) 3 is connected to an arithmetic mode decoder CA. ) 5, and a calculation mode decoder (B) 6 is connected to the calculation unit (B) 4. A gate 10, a register (A) 1 and a register (B) 2 are connected to the calculation result storage register 11, and a comparison circuit 8 and a control device 7 are connected to the latch 9. The control device 7 includes a register 1, a register (B) 2, an operation mode decoder (A) 5,
Operation mode decoder (B) 6, gate 10 and latch 9
is connected. Register (A) 1 is 1 in this embodiment.
Usually one of a register group having multiple registers is used to store the operand.

The operand of this register (A) 1 is sent out via the signal line 12 and taken into the arithmetic units 3 and 4. register(
8) 2 is also usually one of a register group consisting of multiple registers.
is used, the arithmetic number is stored in it, and the signal line 13
The signal is supplied to the arithmetic units 3 and 4 via. The arithmetic mode decoder (A) 5 is for decoding the arithmetic mode command sent from the control device 7 via the signal line 22 and giving it to the arithmetic unit (A) 3 via the signal line 24. Similarly, the arithmetic mode decoder (B) 6 is for decoding the arithmetic mode command sent from the control device 7 via the signal line 23 and giving it to the arithmetic unit (B) 4 via the signal line 25. be. The control device 7 includes the arithmetic mode decoders 5 and 6.
In addition to the operation mode command for A set signal is sent respectively. The arithmetic unit (A) 3 receives the operands sent via the signal line 12 and the operands sent via the signal line 13 based on the arithmetic mode command sent via the signal line 24. A predetermined calculation is performed on the data, and the calculation result is sent to the signal line 14.

Also in the arithmetic unit (B) 4, based on the arithmetic mode command sent via the signal line 25, the operands sent via the signal line 12 and the operands sent via the signal line 13 are calculated. A predetermined calculation is performed on the data, and the calculation result is sent to the signal line 15. At this time, if the calculation mode indicators ◆ sent from the control device 7 to the signal lines 22 and 23 are different, the calculation units 3 and 4 perform different calculations, for example, calculation unit (A) 3 performs addition.
The arithmetic unit (B) 4 can perform subtraction. The comparator circuit 8 receives an arithmetic unit (
The calculation result from A) 3 and the calculation result from the calculation unit (B) 4 sent via the signal line 15 are compared bit by bit, and if all bits match, a result match signal is sent. If they do not match, a result mismatch signal is sent to the signal line 18.

The latch 9 is turned on by a set signal sent from the control device 7 via the signal line 27, when a result match signal is sent via the signal line 18, and when a result mismatch signal is sent. This mode latch is turned off when the latch is on, and the on/off state of this latch is notified to the control device 7 via the signal line 19. Depending on the state of the mode latch 9, for example, if the calculation results do not match, the control device 7 specifies a different calculation mode for the calculation units 3 and 4 and performs the calculation again, thereby preventing malfunction of the calculation units 3 and 4. For now, we will decide whether it is a malfunction in the comparator circuit 8 or not.

On the other hand, the calculation results sent to the signal lines 14 and 15 both enter the gate 10 and are sent from the control device 7 to the signal line 26 to the calculation unit (
A) If the signal to select 3 is being sent, the signal line 14
The calculation result of the calculation unit (A) 3 sent to is latched in the calculation result storage register 11 via the signal line 16, and the signal for selecting the calculation unit (B) 4 is sent to the signal line 26. The operation result of the arithmetic unit (B) 4 sent to the signal line 15 is latched into the operation result storage register 11.

The contents latched in this operation result storage register 11 are as follows:
When the register selection signal is sent from the control device 7 to the register (A) 1 via the signal line 21 (which actually consists of a control line and a data line), the register selection signal is sent via the signal line 17 to the register (A) 1. (A) 1 and the register selection signal is sent to the register (B) 2 via the signal line 20 (also consisting of a control line and a data line). It will be stored. Furthermore, the register (A
) 1 can store data sent from the control device 7 via the signal line 21, and can also send the contents of its own register to the control device 7 via the same signal line 21. Similarly, the register (B) 2 can store data sent from the control device 7 via the signal line 20, and can send the contents of its own register to the control device 7 via the same signal line 20. Therefore, the control device 7 controls each arithmetic unit CA)3, (8)4
The operation result is stored in register CA) 1 or register (B).
2, and can be used to check the normality of operation of each computing unit. After confirming that each of the arithmetic units 3 and 4 operates normally, the control device 7 causes the arithmetic units 3 and 4 to perform different arithmetic operations. It is possible to correctly determine the normality of 8. [Effects of the Invention] As is clear from the above explanation, according to the present invention, the normality of the operation of each computing unit can be checked by arbitrarily selecting and extracting the output of each computing unit and analyzing it with a control device. Furthermore, since it can be confirmed that each arithmetic unit operates normally, a correct normality check of the comparator circuit can be performed, and the reliability of the normality check of the arithmetic unit and the comparator circuit can be greatly improved.

[Brief explanation of drawings]

The figure is a block diagram of an arithmetic processing device showing one embodiment of the present invention. 1...Register (A), 2...Register (B), 3...Arithmetic unit (4), 4...
・Arithmetic unit (B), . 5... Arithmetic mode decoder (4), 6... Arithmetic mode decoder (B),
7...control device, 8...comparison circuit, 9...
...Latch, 10...Gate, 11...
...Arithmetic result storage register.

Claims (1)

[Claims] 1 A register for storing the operands, a register for storing the operands, and an arithmetic unit that performs a predetermined operation on the contents of both registers, and the calculation results of the outputs of the arithmetic units on the two sides are compared. In an arithmetic processing device, the arithmetic processing device includes a comparator circuit that latches the comparison result of the comparator circuit, a computation result storage register that temporarily stores the computation result, and a control device that controls the overall operation. A command from the control device specifies the same arithmetic operation or a different arithmetic operation for the arithmetic units on the two sides, and selects the output of any side of the arithmetic units on the two sides and latches it in the arithmetic result storage register. An arithmetic processing device characterized by: