JPH03142503A - Programmable controller - Google Patents

Abstract

PURPOSE:To diagnose a trouble in real time by comparing the input/output data stored sequentially at control of a control subject with the input/output data obtained at fault and outputting an interruption signal to a microprocessor when the coincidence is obtained between both data. CONSTITUTION:An input/output memory 2 stores the input/output data obtained from a CPU 1 in accordance with the control of a control subject. A trouble status memory 6 sets and stores the state of the input/output data when the control subject has a trouble. A comparator 7 compares the input/output data which are sequentially stored in the memory 2 at control of the subject with the input/output data obtained at fault and stored in the memory 6 in response to the former data. Then an interruption signal is outputted to the CPU 1 when the coincidence is obtained between both data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller that performs failure diagnosis of a controlled object in real time in parallel with control operations of the controlled object.

[Prior Art] FIG. 5 is an overall configuration diagram of a conventional programmable controller having an external failure diagnosis function for controlled objects, etc. In the figure, (1) is a CPU that controls a control target (not shown) according to a sequence program, and (2) is a CPU
(t) is an input/output memory that stores input/output data to be input/output to a controlled object; (3) is an O/S program memory that stores an O/S program for controlling the system of the programmable controller; (4) (5) is a user sequence program memory that stores a sequence program for actually controlling the controlled object; (5) is a failure status memory that stores and stores in advance the input/output program to be input/output when the controlled object fails; (6) is an internal bus that interconnects these programmable controller components.

The failure status memory (5) contains manual data (XO) to (Xn-1) as failure data, as shown in Figure 6.
and output data (Yo) to (Y, -1), m pieces of failure data having a 2n-bit configuration are stored.

Next, the operation will be explained using the flowcharts of FIGS. 5 and 7.

In the programmable controller, after the power is turned on, the CPIJ (1) writes a pattern of input/output data that causes an input/output error, which has been created in advance by a peripheral device, into the failure status memory (6) as failure data (571). bow 1
The user sequence program memory (5
) The sequence program stored in ) is sequentially decoded and branched to each instruction processing routine.572)
Execution of the sequence program is repeated by processing each instruction. When executing a fault diagnosis command in executing a sequence program, the processing routine (573) switches the program execution to a microcomputer program for fault diagnosis, and stores the fault status memory (
6), the failure data is read out (S74). and,
The failure data is compared with the actual input/output data in the input/output memory (2), and if they match, it is regarded as a failure.
Performs error processing (576) and returns. If they do not match, it is considered normal and returns.
Executing the fault diagnosis command in the sequence program as described above ends the external fault diagnosis.

Also, as other prior art, Japanese Patent Application Laid-Open No. 161519/1986
As shown in the above publication, a first storage means stores check items for each check pattern, a second storage means stores reference values corresponding to check items of each pattern for each control state, and a second storage means stores check items for each check pattern. , each time it is confirmed that the failure diagnosis instruction activation condition is met, the first storage means is referred to, each check item of the pattern specified by the failure diagnosis instruction is checked, and the check results are stored in the second storage means. The apparatus is provided with a determination means for determining the presence or absence of a failure by comparing it with a reference value in the control state of the means.

Alternatively, as shown in Japanese Unexamined Patent Publication No. 81-9732, a preset test program for the sequence calculation unit is executed by the sequence calculation unit, and the data obtained after this execution is compared with reference data to obtain the comparison result. A means for determining the operating state of the sequence processing unit is provided, and a switching connection means for connecting the input circuit and the output circuit of the input/output unit is provided, and a means for determining the operating state of the input/output unit is provided. The input circuit and the output circuit are connected by the switching connection means according to the set inspection program for input/output units, and in this state, predetermined data is output to the output circuit and the circuit is connected by the switching connection means. There is a device in which the data input through the input circuit is compared with the output data, and the operating state of the input/output unit is determined from the result of the comparison.

[Problems to be Solved by the Invention] Conventional program controllers have executed failure diagnosis or inspection programs in the manner described above.
The sequence program is switched to the fault diagnosis program at a predetermined cycle, or the fault diagnosis program is switched for the first time when a fault is detected to identify the details of the fault. Therefore, there are problems such as it takes time to detect a fault that occurs during sequence program execution, or the fault is detected after the fault condition has progressed, making it impossible to perform fault diagnosis and fault detection quickly. Ta.

This invention was made to solve the above-mentioned problems.At the same time as the sequence program is executed,
The objective is to obtain a programmable controller that can perform fault diagnosis in real time.

[Means for Solving the Problems] A programmable controller according to the present invention includes a microprocessor that controls a controlled object according to a sequence program, and includes an input/output memory that stores input/output data input and output from the microprocessor. , a failure status memory that sets and stores the state of the input/output data at the time of a failure of the controlled object, input/output data sequentially stored in the input/output memory when controlling the controlled object, and the failure corresponding to the input/output data. The comparator compares the failure input/output data in the status memory and outputs an interrupt signal to the microprocessor when the data match is determined.

[Effect]

According to this invention, the comparator compares the input/output data written to the input/output memory simultaneously with the execution of the sequence program and the failure data written to the failure status memory asynchronously with the execution of the sequence program. At regular times, a failure is determined and an interrupt signal is generated to the microprocessor for executing the sequence program.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figures, from (1) to (6), the same numbers as in FIG. 3 indicate the same things.

(7) is a comparison circuit, and failure status memory (6)
The contents of the input/output memory (2) are compared with the contents of the input/output memory (2), and an interrupt is generated. Further, a specific example of the data in the failure status memory (6) is shown in FIG. 2 as well as in FIG. 6.

Details of the comparator circuit (7) in FIG. 1 are shown in FIG. 3. 8 is an interrupt enable/disable register that compares the data in the failure status memory (6) and the input/output data in the input/output memory (2) and determines whether or not to generate an interrupt. (
9) is an interrupt status flag that compares the data in the fault status memory (6) and the input/output data in the input/output memory (2) and determines which fault data causes the generated interrupt. This is a logic circuit for specifying interrupt signal generation and failure data.

Next, the operation will be explained using the flowcharts of FIGS. 1, 2, 3, and 4.

After the power is turned on, the CPU (1) reads failure data 1, 2, . . . . m is stored in the failure status memory (6), all interrupt status registers are set to O, and the interrupt enable/disable register is set to enable (S41). Subsequently, the sequence program is sequentially decoded from the user sequence program memory (5), branched to each instruction processing routine (542), and execution is repeated by processing each instruction (S43). The comparison circuit (7) compares failure data 1, 2, . ...ml each (2
n bits) and input/output data (2) in the input/output memory (2)
n bits) at the same time.

In this comparison operation, 2n-bit failure data is input to one input terminal of the 20 ExNOR circuits, and the same <2n-bit input/output data is input to the other input terminal. At this time, if a failure occurs in the controlled object and 2n-bit input/output data with the same bit configuration as the failure data is input manually, EXN
The OR circuit outputs a "1" level signal to one input terminal of the AND circuit. The other input terminal of this AND circuit receives a bit signal of 1" or "O" indicating whether or not to output an interrupt signal to CPU (1) when the above failure occurs. ) is input.

For example, if the ExNOR circuit output is 1" and the interrupt enable/disable signal is set to "1", the AND circuit outputs a 1" level signal to CPIJ (1) through the OR circuit,
Use as an interrupt signal. Further, the interrupt status register (9) which receives the input of the AND circuit writes "1" as information indicating which fault data is caused.

At this time, CPU (i) branches to an interrupt processing routine. In this routine, the interrupt status register (9) is used to diagnose which fault data is causing the fault (544).

Next, the information is transmitted to peripheral devices or LEDs via the bus (4) (S45).Also, in the above embodiment, only failure diagnosis was explained, but it is also possible to try to grasp a specific state as the state changes. A debugger or the like may be used, and the same effect as in the above embodiment can be achieved. Further, although the failure data is given to the failure status register, it is also possible to give the data as normal data and detect the failure by generating an interrupt due to a mismatch, and the same effect as in the above embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, since the external fault 1m diagnosis is always performed asynchronously with the execution of sequence commands, the fault diagnosis can be performed in real time, and the fault can be detected early. This has the effect of improving the diagnostic function and further increasing the reliability of failure detection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a programmable controller according to an embodiment of the present invention, FIGS. 2 and 3 are partial detailed explanatory diagrams of the programmable controller, and FIG. 4 is for explaining the fault diagnosis function in this embodiment. 5 is a configuration diagram of a programmable controller according to the prior art, FIG. 6 is a partial detailed explanatory diagram thereof, and FIG. 7 is an operation flowchart thereof. In the figure, (1) is a CPU, (2) is an input/output memory, (6) is a failure status memory, and (7) is a comparison circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a programmable controller equipped with a microprocessor that controls a controlled object according to a sequence program, an input/output memory stores input/output data input and output from the microprocessor as the controlled object is controlled, and a A fault status memory that sets and stores the state of input/output data, input/output data sequentially stored in the input/output memory during control of a controlled object, and input/output at the time of failure in the fault status memory corresponding to the input/output data. A programmable controller comprising: a comparator that compares data and outputs an interrupt signal to the microprocessor when determining data coincidence.