JPH03186956A - Cpu bus data diagnosis device - Google Patents

Abstract

PURPOSE:To detect the error of data which CPU fetches by inspecting data which is the same as data that CPU fetches. CONSTITUTION:The output of a CRC calculation part 4 and the output of a CRC storage part 6 are inputted to respective inputs of a comparator 5 with two inputs and they are compared. When they do not coincide, the comparator outputs an error signal 10. The connection of a data bus change over switch is changed over by the error signal 10 and the second input is connected. Namely, a jump instruction storage part 3 where an instruction for reducing a program counter 1 by one step is stored is connected to the data bus 8 of CPU 1. When a subsequent machine cycle starts, CPU 1 executes the instruction. Thus, the address of the same data memory as that where the error occurs is outputted from the program counter. Thus, a retry as against the occurrence of the error is executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a CPU bus data diagnostic device, and more particularly, to a CPU bus data diagnostic device that makes it possible to fetch the same bus data again even when an error is detected in the bus data. Regarding.

(Technological Environment) Modern microprocessors have been developed with capabilities that exceed those of traditional minicomputers, and the tasks that these microprocessors must accomplish have become more sophisticated.

Moreover, their use is still mostly in the field of mechatronics, where highly reliable operation in very harsh noise environments is required.

Therefore, when designing these systems, it is necessary to make efforts to suppress the generation of noise, and at the same time, it is desirable that the microprocessor itself be designed to be resistant to noise.

[Conventional technology]

As a conventional technique, there is a technique that performs a parity check on memory data.

FIG. 2 shows the structure of a memory with parity check, which is an example of the prior art.

In the figure, a CPU, memory, and parity check unit 4 are connected to each other via a data bus 5. In addition to the memory for data, a parity memory 3 is prepared.

Explain the operation.

Correct parity is written in the parity memory 3 in advance. When the bus direction is from memory to CPLJI, parity check 4 calculates parity and writes it to parity memory 3.

Conversely, when the bus direction is from the CPUI to the memory, parity is calculated from the data on the bus, and at the same time, harness is read from the parity memory 3, the two are compared, and if they do not match, an error signal is output.

This error signal generates an interrupt to the CPU. After that, the interrupt processing program fetches the same bus data again.

[Problem to be solved by the invention]

The conventional bus data diagnostic device described above has the disadvantage that it cannot detect errors in data fetched by the CPU because it is attached to the memory side. Another disadvantage is that it takes time and effort to create a program in order to fetch the same bus data again.

[Means to solve the problem]

The CPU bus data diagnostic device of the present invention temporarily stores the calculation results of the cRct+ calculation section connected to the data bus and the CRC calculation section and outputs them to the CR and C buses, or
CR, C that temporarily stores the CRC signal from the RC bus
The output of the storage section and the CRC calculation section is taken as the first input, and the output of the CRC storage section is taken as the second input.
a comparator that compares the coincidence of inputs and outputs an error signal if they do not match; the data bus is a first input;
A data bus changeover switch whose output is connected to a data bus on the CPU side and is switched by the output of the comparator; and a data bus changeover switch connected to a second input of the databus changeover switch, which stores an instruction to decrement the program counter by one step. and a jump instruction storage section.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

A CRC storage section 6 connected to the data bus 8 that temporarily stores the CRC calculation result and outputs it to the CRC bus 9, or temporarily stores the CRC signal from the CRC bus 9. A comparator that uses the 4 inputs for CRC calculation as the first input and the output of the CRC storage unit 6 as the second input, compares the two inputs to see if they match, and outputs an error signal if they do not match. 5 and data bus 8 to the first
The output is connected to the data bus 8 on the CPU 1 side, and is connected to a data bus changeover switch that is switched by the output of the comparator 5, and the second input of the databus changeover switch, and the output is connected to the data bus 8 on the CPU 1 side. It consists of a jump instruction storage section 3 in which instructions to perform are stored.

Next, the operation will be explained.

Correct CRC data is written in the CRC memory 7 in advance. In addition, the data bus changeover switch is the first one.
is connected to the input of

When the direction of the data bus is from the CPU 1 to the memory, data output from the CPU I is input to the data memory unit 2 via the data bus changeover switch for CRC calculation purposes.

CRC Calculation The CRC is calculated on the input data. The result is written to the CRC memory 7 via the CRC bus 9.

Conversely, when the direction of the data bus 8 is from the data memory section-2 to the CPUI, the data on the data bus 8 is input to the CPU and the CRC calculation section 4 in one main cycle.

The CLC calculation unit 4 calculates the CRC for this data. CR read out from CR and C memory 7 at the same time
The C data is stored in the CRC storage section 6.

The output of the CR,C calculation section 4 and the output of the CRC storage section 6 are 2.
The signals are input to respective inputs of the input comparator 5 and compared.

If there is no match, the comparator outputs an error signal 1o.

The data bus changeover switch is changed in connection by this error signal 10, and its second input is now connected. That is, the jump instruction storage unit 3 in which the instruction to decrement the program counter by one step is stored in the CP 1. J ] data bus 8.

When the next machine cycle begins, the CPU 1 executes this instruction so that the same data memory address that caused the error is output from the program counter. As a result, a retry is executed in response to the occurrence of an error.

〔Effect of the invention〕

Since the CPU bus data diagnostic device of the present invention fetches data from the CPU and inspects it,
This has the effect of being able to detect errors in data fetched by the PU. Furthermore, since only one instruction that can directly control the program counter is prepared in hardware, there is no need to create a program to fetch the same bus data again.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. DESCRIPTION OF SYMBOLS 1... CPU, 2... Data memory, 3... Jump instruction storage part, 4... CPU calculation part, 5... Comparator, 6... CRC storage part, 7... CRC memory, 8
...Data bus, 9...CRC bus, 10...Error signal.

Claims (1)

[Claims] Cyclic code (hereinafter abbreviated as CRC) connected to the data bus
A calculation unit and the calculation result of the CRC calculation unit are temporarily stored and output to the CRC bus, or the CRC calculation result from the CRC bus is
A CRC storage section that temporarily stores signals and the output of the CRC calculation section are used as the first input, and the output of the CRC storage section is used as the second input.The two inputs are compared to see if they match.If they do not match, an error occurs. a comparator that outputs a signal; a data bus changeover switch whose first input is the data bus and whose output is connected to a data bus on the CPU side and which is switched by the output of the comparator; and a second data bus changeover switch of the data bus changeover switch. A CPU bus data diagnostic device comprising a jump instruction storage section connected to an input and storing an instruction for decrementing a program counter by one step.