JP2720580B2 - Fault-tolerant computer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault-tolerant computer, and more particularly, to a fault-tolerant computer having a redundant control circuit check function.

[Conventional technology]

As shown in FIG. 5, the conventional fault tolerant computer fetches instructions from the memory and executes them. The normal mode CPU 51 monitors the address bus, the data bus, and control signals. It has an external circuit 53 that inputs a detection signal and outputs a CPU freeze signal that stops the operations of both CPUs.

Next, the operation will be described.
Fetch instructions from memory and execute. Monitoring mode CPU52
Compares the address bus, control signal, and data on the data bus output by the normal mode CPU 51 in each bus cycle with the internal state, and outputs a mismatch detection signal when a mismatch occurs. The external circuit 53 receives the mismatch detection signal, outputs a CPU freeze signal before the CPU malfunctions, and stops both CPUs.

[Problems to be solved by the invention]

In this conventional fault-tolerant computer, the monitoring function of the monitoring mode CPU has no means to intentionally generate a mismatch between the normal mode CPU and the monitoring mode CPU to confirm that it is operating normally. Was difficult. Also, even if the monitoring function is operating normally, directly connecting I / O that changes data even during a read cycle on the data bus may not satisfy the data setup time of the CPU. However, there is a problem that hardware design and software design are significantly restricted.

[Means for solving the problem]

The fault tolerant computer of the present invention
A normal mode CPU that executes instructions, a monitoring mode CPU that monitors the operation of the normal mode CPU, and when a mismatch is detected by the monitoring mode CPU, a mismatch detection signal is input and the operations of both CPUs are stopped. Prior art fault tolerant circuit having an external circuit for outputting a freeze signal
In addition to the computer, it has a latch circuit that captures data in synchronization with a clock supplied to the CPU during a data read cycle, and a buffer circuit that captures data asynchronously with the clock supplied to the CPU during a system test. I have.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The same normal mode CPU 11 fetches an instruction from the memory 17 and executes it. The monitoring mode CPU 12 compares the address bus, the data bus, and the control signal with the internal state, and outputs a mismatch detection signal when a mismatch is detected. The external circuit 13 inputs the mismatch detection signal, and outputs the normal mode CPU 11, the monitoring mode CP
A CPU freeze signal or an interrupt signal for stopping the operation of the CPU is output to U12. During the I / O read cycle, the latch circuit 14 captures data from the I / O 16 in synchronization with the CPU reverse-phase clock, and the normal mode CPU 11 and the monitor mode C
Communicate to both PU12. The buffer circuit 15 operates in the normal mode C during a memory write cycle and an I / O write cycle.
The data output from the PU 11 is transmitted to the memory 17 and the I / O 16, and during a memory read cycle, the data from the memory 17 is transmitted to both the normal mode CPU 11 and the monitoring mode CPU 12.

Next, the operation of the circuit of FIG. 1 will be described with reference to the waveform diagrams of FIGS. 2 and 3 and the program flowchart of FIG. FIG. 2 shows the normal mode CPU 1 shown in FIG.
It is a waveform diagram of an operation example at the time of the read cycle of 1.The normal mode CPU 11 operates in synchronization with the CPU clock, starts the cycle at T1, passes the T2, and recognizes the ready signal at the TW. , The data at that time is read, and the cycle ends. The monitoring mode CPU 12 also internally performs the same operation. A point on the time axis for reading this data is called a data sample point. Normal mode CPU 11 and monitoring mode C
The PU 12 requires a unique data setup time for this data sample point due to the characteristics of the semiconductor device. That is, if the data is not finalized before the data setup time from the data sample point,
The operations of the normal mode CPU 11 and the monitoring mode CPU 12 are not guaranteed.

Normally, a wait is inserted for read access to I / O and memory with slow response.
Since it is assumed that U11 and the monitoring mode CPU 12 read the data, it seems that only the buffer circuit 15 is sufficient for the data bus line. FIG. 3 is a data read timing waveform diagram of general I / O. In FIG. 3, if data does not change during the data determination period, only the buffer circuit 15 is sufficient for the data bus line as described above. There are many things that change data. In this case, if the data change point is shorter than the data setup time for the data sample point in FIG.
Even if there is no failure, operation mismatch may occur.

FIG. 4 shows a program flowchart in which a CPU mismatch operation easily occurs when such an I / O is used. In the case of this I / O, after accepting a command once, information on whether the next command can be accepted is placed on the data line at the time of the I / O read cycle, but the information changes as soon as it can be accepted Therefore, data is updated even during the I / O read cycle. Therefore, when there is a continuous command request, if the data indicating that the next command can be accepted changes to less than the data setup time with respect to the data sample point in FIG.
The normal mode CPU 11 recognizes that this I / O can accept the next command, but the monitoring mode CPU 12 may recognize that the I / O cannot accept the next command. In this case, the condition branch destinations of the two CPUs are different, and the monitoring mode CPU 12 detects a mismatch.

Therefore, in order to avoid this, the latch circuit 14 in FIG. 1 is required. Since the latch circuit 14 takes in data at the rising edge of the opposite phase clock of the CPU clock, the data setup time of the normal mode CPU 11 and the monitoring mode CPU 12 is satisfactory even if the I / O 16 changes the data during the read cycle. Let me do. Also, at the time of system inspection, if a mismatch is detected by intentionally using the buffer circuit 15 in the I / O read cycle, it can be verified that the monitoring function of the monitoring mode CPU 12 is operating normally.

〔The invention's effect〕

As described above, the present invention provides a data bus line with a latch circuit that captures data in synchronization with a clock and a buffer circuit that transmits the data asynchronously with the clock. In a normal operation state, the latch circuit is used during an I / O read cycle. In the memory read, write cycle, and I / O write cycle, the buffer circuit is selected, so that I / O that changes data even during the read cycle can be used, simplifying hardware design. Has an effect. Also, at the time of system inspection, even in the I / O read cycle, the use of the buffer circuit has an effect that the verification that the monitoring function of the monitoring mode CPU is operating normally can be easily performed. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a read cycle timing chart of the normal mode CPU 11 shown in FIG. 1, and FIG. 3 is a read cycle timing of general I / O. FIG. 4 is a waveform diagram showing the case where the I / O that changes data during the data read cycle is used.
FIG. 5 is a block diagram of a conventional fault-tolerant computer, in which a monitoring mode CPU 12 shown in FIG. 11: Normal mode CPU, 12: Monitoring mode CPU, 13: External circuit, 14: Latch circuit, 15: Buffer circuit, 16 ...
... I / O, 17 ... Memory, 51 ... Normal mode CPU, 52 ... Monitor mode CPU, 53 ... External circuit.

Claims (1)

(57) [Claims] 1. A normal mode microprocessor for executing an instruction, a monitor mode microprocessor for monitoring the operation of the normal mode microprocessor, and a mismatch detection signal when an operation mismatch is detected by the monitor mode microprocessor. And a fault-tolerant computer having an external circuit that outputs a freeze signal for stopping the operation of both microprocessors, the normal mode microprocessor and the monitoring mode microprocessor use the same address bus, data bus, and control signal. Shared, data read and data bus
During a cycle, a latch circuit that takes in data in synchronization with a clock supplied to a microprocessor, a buffer circuit that takes in data asynchronously with this clock, and an I / O that changes data during a read cycle for inspection
O, at the time of system inspection, by taking in data from the buffer circuit asynchronously with the clock,
A fault-tolerant computer which intentionally causes a mismatch between the operations of the two microprocessors and makes it possible to verify that the monitoring function of the monitoring mode microprocessor is operating normally.