JPS5821281B2 - arithmetic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device using a processor such as a microcomputer.

With recent advances in digital circuit technology, microcomputers and other processors have become smaller and more affordable, and as a result, microcomputers are being introduced into various analog devices, including controllers. Attempts are being made to do so.

In this case, since the processor performs various calculations or various tasks in a time-sharing manner, the processor may malfunction or peripheral circuits connected to the processor, such as D/A
It is unacceptable for the converter or analog signal holding means to fail.

Conventionally, as a method for determining whether the operation of a processor itself is normal or abnormal, a method of executing a self-diagnosis program has generally been used.

However, this method has the disadvantage that a special self-diagnosis program must be prepared and that the execution of this program takes up a lot of time.

In the present invention, the peripheral circuits of the processor are checked on the assumption that the processor is operating normally;
If each peripheral circuit is operating normally, a pulse signal is output.

By detecting the presence or absence of this pulse signal with a pulse detector provided separately from the processor, it is possible to determine whether the processor itself is operating normally or abnormally.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment exemplifies an arithmetic device that receives an analog signal as an input and outputs an arithmetic result as an analog signal.

In the figure, 10 is an input terminal to which the analog signal ex to be operated is applied, and R1 and R2 are resistors connected in series between the input terminal 10 and a common line, which constitute voltage dividing means for dividing the voltage of the signal to be operated ex. ing.

11 to 14 are comparators, respectively, and 20 is a processor which inputs signals from each comparator, such as a microcomputer.

Reference numeral 30 denotes a D/A converter that converts the digital signal from the processor 20 into an analog signal, and supplies its output in common to one input terminal of each of the comparators 11 to 14, as well as to an analog signal holding means 40, which will be described later. be.

The analog signal holding means 40 includes semiconductor switches 41 . It consists of a capacitor 42 and an amplifier 43.

50 is a pulse detection circuit that receives a pulse signal output from the processor 20 as an input and detects the presence or absence of this pulse signal.
ABLE MONOMULTI) circuit is used.

44 is an output terminal for the calculation result, and 51 is an output terminal for the alarm signal.

The comparator 11 has one input terminal connected to D/
A reference voltage erf is given from the A converter 30,
The comparator 12 also receives a signal e from the analog signal holding means 40 via a lead wire 45 at one input end.

is given. Further, one input terminal of the comparator 13 receives an analog signal to be operated on.

ex is given, and one input terminal of the comparator 14 receives a divided voltage signal ex/n (
n = −Jl−) is given.

These ratio R1+R2 comparators 11 to 14 compare the signal applied to one input end with the analog signal ef from the D/A converter 30 applied to the other input end, and The comparison result is used as an input signal to the processor 20.

The processor 20 has an input port 21, e.g.
It is composed of a data memory section 22 composed of a write memory, a settlement control section 23, a program memory section 24 composed of, for example, a read-only memory, and an output port 25.

The input port 21 is supplied with signals from the comparators 11 to 14, and is supplied with a signal from the arithmetic control section 23.
Waiting for output signals to be read sequentially or selectively.

The data memory section 22 temporarily stores a signal applied from the input port 21, for example, according to a signal from the calculation control section 23, and stores calculation results.

The program memory section 24 stores in advance conversion procedures for converting analog signals into digital signals, procedures for controlling peripheral circuits, various calculation procedures, and data necessary for calculations, and the contents thereof are used for calculation control. Part 23
It is read out by the signal from.

The arithmetic control section 23 reads the state of the signal applied to the input port 21, writes it to the data memory section 22, decodes the arithmetic procedure from the program memory section 24, and reads the data read from there and the data memory. Part 2
Digital operations are performed using the signals read from 2.

The output port 25 is supplied with a digital signal output from the data memory section 22 or the arithmetic control section 23, and is connected to the D/A converter 30 by the signal from the arithmetic control section 23.
A digital signal is output to the signal holding circuit 40, or a control signal for controlling this circuit is output to the signal holding circuit 40.

The D/A converter 30 converts the digital signal output from the output port 25 into an analog signal, and converts this into an analog signal to the comparator 11.
When the switch 41 is made conductive by an output command signal (control signal) from the processor 20, it is output to the analog signal holding means 40.

Next, the self-checking operation of the device configured in this way will be explained in the second step.
This will be explained with reference to Frosede in the figure.

In the present invention, it is assumed that the processor 20 is operating normally, and first checks whether the operation of the peripheral circuit is normal or abnormal, and if it is normal, outputs a pulse signal, and detects the presence or absence of this pulse signal. It is characterized by determining whether the operation of peripheral circuits and processors is normal or abnormal.

[Check 1] In this procedure, comparators 13, 14 . processor 20,
Check whether the D/A converter 30 is operating normally.

In this case, the processor 20 uses a signal (program) written in the program memory section 24, for example.
Accordingly, the output signal from the comparator 13 is read, and an analog-to-digital conversion loop composed of the comparator 13, the processor 20, and the D/A converter 30 converts the operand signal ex given to the input terminal of the comparator 13. Convert to digital signal.

Although there are various methods for converting an analog signal into a digital signal, for example, a successive approximation method can be used to easily convert the analog signal into a digital signal.

The converted digital signal is written into a part of the data memory section 22 as EX, for example.

Processor 20 then reads the output signal from comparator 14 and in turn reads the output signal from comparator 14, processor 20 and D/
The analog-to-digital conversion loop constituted by the A converter 30 converts the divided voltage signal ex/n applied to the input terminal of the comparator 14 into a digital signal. is written as EX/n.

Next, the processor 20 uses EX and EX/n stored in the data memory section 22 to perform a predetermined operation, for example, a division operation, according to the self-check program stored in the program memory section 24. EX and E
)(Find the ratio of /n.

The procedure used to calculate the ratio depends on the content of the program, but it is preferable to go through various calculation procedures from the standpoint of checking various calculation functions.

division. As a result of the calculation, the answer is n or 1/n, assuming that the analog-to-digital conversion loop and various calculation functions are operating normally.

Therefore, the processor 20 determines that the calculation result is n or 1.
/n, it is possible to self-check whether the function of the processor 20 and the operation of the loop including the comparators 13, 14 and the D/A converter 30 are normal or abnormal over the entire input range. .

In Check 1, if an abnormality is detected, the check program terminates, and if no abnormality is detected,
Move on to check 2.

[Check 2] Here, the processor 20 checks the function of the D/A converter 30.

In this case, the processor 20 reads the output signal from the comparator 11, and the comparator 11, the processor 20 and the D/
An analog-to-digital conversion loop constituted by the A converter 30 converts the reference voltage erf applied to one input terminal of the comparator 11 into a digital signal.

Then, by determining whether this value is within a predetermined value range, it is checked whether the D/A converter 30 is functioning normally.

In check 2, if an abnormality is detected, the check program ends, and if no abnormality is detected, the procedure moves to check 3.

When checking the reference voltage erf itself, use another reference e/rf to A/D convert this voltage and read it into the processor.
f can be checked.

[Check 3] Here, the processor 30 uses the analog signal holding means 40
Check whether the operation is normal.

In this case, the processor 20 outputs a certain digital value (for example, a calculated value) to the analog signal holding means 40 via the D/A converter 30.

Also, the output value e of this analog signal holding means 40.

is read through the comparator 12, and the analog signal holding means 4
0 output value e.

Convert to digital signal.

This value is then compared with the digital value output by the processor 20 to the D/A converter 30, and it is determined whether the two are approximately equal (or have corresponding values).

This checks whether the analog signal holding means 40 is operating normally.

In check 3, if no abnormality is detected, the processor 20 performs an operation to output a pulse signal to the pulse detection circuit 50.

That is, check 1. Check 2. If no abnormality is detected in any of the steps in check 3, a pulse signal is output, and if an abnormality is detected in any of the steps, no pulse signal is output.

Check above 1. Check 2. The check program consisting of check 3 is executed every time the main program that instructs the calculation procedure etc. ends, as shown in FIG. As shown in FIG. 3, when the check program is completed, a pulse signal is output to the pulse detection circuit 50.

The pulse detection circuit 50 receives a constant period T from the processor 20.
(corresponding to the cycle in which the check program is repeated), and if this pulse signal is output, that is, no abnormality is detected in each check, and the pulse signal is not detected in the processor 20. If the outputting operation is also performed normally, a bi-level signal, for example, indicating the normal state of the device is outputted to the terminal 51 as shown in FIG.

On the other hand, if an abnormality is detected in any of the checks, or if there is an abnormality in the operation of outputting the pulse signal in the processor 20, the pulse signal is not output as shown in part a of FIG.

The pulse detection circuit 50 detects the disappearance of this pulse signal and outputs, for example, a low level signal indicating an abnormal state of the device.

Therefore, by the signal obtained from the terminal 51, it is possible to easily determine whether the operation of the peripheral circuits of the processor is normal or abnormal, and at the same time whether the operation of the processor itself is normal or abnormal.

In addition, in the above explanation, the check program may be executed before the main program, and in this check program, the order of checks 1 to 3 may be different from the order shown in FIG. But that's fine.

Also, in the flowchart in Figure 2, for example, check 1
In this case, if an abnormality is detected, checks 2 and 3 are skipped and the check program is terminated. However, if an abnormality is detected, for example, the abnormality flag is set to II II II, Continue checking 2,
3 may be executed.

In this case, after check 3 is completed, the processor may perform an operation to output a pulse signal when all abnormality flags are not II III II.

FIG. 4 is a block diagram showing another embodiment of the present invention.

In this embodiment, a multiplexer 15 for switching various analog signals and an A/D converter for converting the signal selected by the multiplexer 15 into a digital signal are provided on the input side of the processor 20. It is provided to the processor 20.

Also, a switch is placed on the output side of the analog signal holding means 40)
60 is provided, and this switch 60 is driven by the output signal of the pulse detection circuit 50, so that if an abnormality occurs, control is performed on the safe side.

Further, when an abnormality occurs, the alarm means 61 is driven.

Note that in this embodiment, if the A/D converter 16 is provided for each input signal, the multiplexer 15 becomes unnecessary.

As explained above, according to the device of the present invention, a check program for the peripheral circuit is executed to output a pulse signal only when normal, and the presence or absence of this pulse signal is detected. At the same time as checking the peripheral circuits, it is also possible to check for abnormalities in the processor's own operation, such as if a port that outputs a normal or abnormal signal is abnormal, or if the main program does not execute the check program due to looping or the like.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, FIG. 2 is a flowchart of the self-checking operation of the device shown in FIG. 1, FIG. 3 is an explanatory diagram of the operation, and FIG. FIG. 10... Input terminal, R1, R2... Resistance voltage dividing means,
11-14...Comparator, 20...Processor, 30
. . . D/A converter, 40 . . . Analog signal holding means, 50 . . . Pulse detection circuit.

Claims (1)

[Claims] 1. A microprocessor, a D/A converter that converts a digital signal from the microprocessor into an analog signal, an analog signal holding means that holds the analog signal from the D/A converter, and a signal to be operated on. and a first signal reading means for reading the divided voltage signal of the operated signal;
a second signal reading means for reading the reference voltage of the /A converter, a third signal reading means for reading the output signal of the analog signal holding means, and a pulse signal detecting means, a first operation of performing a predetermined operation on the operated signal; and a first operation of dividing the operated signal read through the first signal reading means and the divided voltage signal and determining whether the operation result is a predetermined value. a second checking operation for determining whether or not the reference voltage read through the second signal reading means is within a predetermined value range; to the analog signal holding means through the third signal reading means, and reading the output of the analog signal holding means at that time through the third signal reading means to determine whether or not the read value corresponds to the output digital value. a third check operation, and the first, second . Periodically performs an operation of outputting a pulse signal to the pulse signal detection means when it is determined to be normal in each third check operation, and the pulse signal detection means detects the pulse signal periodically output from the processor. An arithmetic device characterized in that it outputs a signal indicating a normal state when the periodic pulse is detected, and outputs a signal indicating an abnormal state when the periodic pulse is not detected.